Semiconductor devices fabricated by doped material layer as dopant source

ABSTRACT

A method of forming a semiconductor device is provided, in which the dopant for the source and drain regions is introduced from a doped dielectric layer. In one example, a gate structure is formed on a semiconductor layer of an SOI substrate, in which the thickness of the semiconductor layer is less than 10 nm. A doped dielectric layer is formed over at least the portion of the semiconductor layer that is adjacent to the gate structure. The dopant from the doped dielectric layer is driven into the portion of the semiconductor layer that is adjacent to the gate structure. The dopant diffused into the semiconductor provides source and drain extension regions.

CROSS REFERENCE TO RELATED APPLICATION

This application is a divisional of U.S. patent application Ser. No.12/819,440, filed Jun. 21, 2010, the entire content and disclosure ofwhich is incorporated herein by reference.

DESCRIPTION Background

The present disclosure relates to semiconductor devices and methods offorming semiconductor devices.

For more than three decades, the continued miniaturization of siliconmetal oxide semiconductor field effect transistors (MOSFETs) has driventhe worldwide semiconductor industry. Various showstoppers to continuedscaling have been predicated for decades, but a history of innovationhas sustained Moore's Law in spite of many challenges. However, thereare growing signs today that metal oxide semiconductor transistors arebeginning to reach their traditional scaling limits. Since it has becomeincreasingly difficult to improve MOSFETs and therefore complementarymetal oxide semiconductor (CMOS) performance through continued scaling,methods for improving performance without scaling have become critical.

SUMMARY

In one embodiment, a method of providing a semiconductor device isprovided, in which the dopant for the source and drain extension regionsis introduced from a doped material layer, such as a doped dielectriclayer. In one example, a gate structure is formed on a semiconductorsurface of a substrate. A doped dielectric layer is formed over at leastthe portion of the semiconductor surface that is adjacent to the gatestructure. The dopant from the doped material is driven into the portionof the semiconductor surface that is adjacent to the gate structure. Thedopant provides source and drain regions in the semiconductor surface.The doped material layer is removed to expose the semiconductor surface.Raised source and drain regions are formed on the semiconductor surfaceon opposing sides of the gate structure.

In yet another embodiment, a method of forming a finFET is provided thatincludes forming a gate structure on a portion of a fin structure,wherein exposed portions of the fin structure are present on opposingsides of the gate structure. The fin structure includes a fin cappresent on the upper surface of a semiconductor material. Spacers areformed on the sidewall of the fin gate structure. A doped dielectriclayer is formed on exposed portions of the semiconductor material of thefin structure that are adjacent to the gate structure. The dopant fromthe doped dielectric layer is driven into the exposed portions of thesemiconductor material of the fin structure on opposing sides of thegate structure. The dopant provides source and drain extension regionsin the semiconductor material of the fin structure. The doped dielectriclayer is removed. Raised source regions and raised drain regions areformed on the exposed portions of the semiconductor material of the finstructure. The source regions and the drain regions may merge each otherafter raised source/drain process.

In another embodiment, a method of forming a complementary metal oxidesemiconductor (CMOS) device is provided. In one example, the methodincludes providing a semiconductor substrate having a first region and asecond region. Forming a first gate structure in the first region of thesemiconductor substrate and a second gate structure in the second regionof the semiconductor substrate. A first material layer doped with afirst conductivity type dopant is formed over the first region of thesemiconductor substrate, and a second material layer doped with a secondconductivity type dopant is formed over the second region of thesemiconductor substrate. The first conductivity type dopant is of anopposite conductivity than the second conductivity type dopant. Thefirst conductivity dopant is diffused into the first region of thesemiconductor substrate on opposing sides of the first gate structure,and the second conductivity type dopant is diffused into the secondregion of the semiconductor substrate on opposing sides of the secondgate structure. The first conductivity type dopant that is diffused intothe first region of the semiconductor substrate provides a firstconductivity type source extension region and drain extension region.The second conductivity type dopant that is diffused into the secondregion of the semiconductor substrate provides a second conductivitytype source extension region and drain extension region. The firstmaterial layer and the second material layer are removed. Raised sourceand drain regions are formed on the upper surface of the semiconductorlayer on opposing sides of the gate structure.

In another embodiment, a semiconductor device is provided including asource region and a drain region that are present in a single crystalsemiconductor layer having a thickness of less than 10 nm. In oneembodiment, the semiconductor device includes a gate structure on afirst portion of a semiconductor layer having a thickness of less than10 nm. Source regions and drain regions are formed in the semiconductorlayer on opposing sides of the gate structure, in which the sourceregions and drain regions extend an entire thickness of thesemiconductor layer. The crystal structure of the source region and thedrain region in the semiconductor layer is substantially damage-free.

In another embodiment, a finFET device is provided that includes a gatestructure on a portion of a fin structure having a width of less than 10nm. The fin structure includes a dielectric cap present on asemiconductor material, wherein exposed portions of the fin structureare on opposing sides of the gate structure. Source and drain extensionregions are present in the semiconductor material of the fin structureon opposing sides of the gate structure. The source and drain extensionshave a crystal that is substantially damage-free.

DESCRIPTION OF THE DRAWINGS

The following detailed description, given by way of example and notintended to limit the invention solely thereto, will best be appreciatedin conjunction with the accompanying drawings, wherein like referencenumerals denote like elements and parts, in which:

FIG. 1 is a side cross-sectional view of forming a first gate structurein a first region of the semiconductor substrate and a second gatestructure in a second region of the semiconductor substrate, inaccordance with one embodiment of the present disclosure.

FIG. 2 is a side cross-sectional view of depositing a first materiallayer doped with the first conductivity type dopant on the first regionand the second region of the semiconductor substrate, and forming atleast one dielectric layer on the first material layer doped with thefirst conductivity type dopant, in accordance with one embodiment of thepresent disclosure.

FIG. 3 is a side cross-sectional view depicting forming a block mask onthe at least one dielectric layer in the first region, and etching anexposed portion of the at least one dielectric layer and an underlyingportion of the first material layer doped with the first conductivitytype dopant selective to the block mask to expose at least thesemiconductor layer in the second region of the semiconductor substrate,in accordance with one embodiment of the present disclosure.

FIG. 4 is a side cross-sectional view depicting removing the block mask,and depositing the second material layer doped with the secondconductivity type dopant in direct contact with a remaining portion ofthe at least one dielectric layer in the first region and in directcontact with the semiconductor layer in the second region of thesemiconductor substrate, in accordance with one embodiment of thepresent disclosure.

FIG. 5 is a side cross-sectional view depicting driving the firstconductivity dopant from the first material layer into the first regionof the semiconductor substrate, and driving the second conductivity typedopant from the second material layer into the second region of thesemiconductor substrate, in accordance with one embodiment of thepresent disclosure.

FIG. 6 is a side cross-sectional view depicting forming raised sourceand drain regions on the upper surface of the semiconductor layer onopposing sides of the gate structure, and forming metal semiconductoralloy regions, in accordance with one embodiment of the presentdisclosure.

FIG. 7 is a flow chart illustrating the process of another embodiment ofa method in accordance with the present disclosure, in which thesubstrate is a bulk-semiconductor substrate.

FIG. 8 is a side cross-sectional view depicting a final semiconductorstructure including a bulk semiconductor substrate, in accordance withone embodiment of the present disclosure.

FIG. 9 is a side cross-sectional view depicting a final semiconductorstructure including a bulk semiconductor substrate having strained wellregions present therein, in accordance with one embodiment of thepresent disclosure.

FIG. 10 is a perspective view depicting an initial structure including afirst fin structure and a second fin structure, as used in oneembodiment of a method for forming a finFET device.

FIG. 11 is a perspective view depicting forming a first gate structureon a first fin structure and a second gate structure on a second finstructure, in accordance with one embodiment of the present disclosure.

FIG. 12 is a perspective view depicting forming a first spacer in directcontact with the first and second gate structures, in accordance withone embodiment of the present disclosure.

FIG. 13 is a perspective view of depositing a first material layer dopedwith the first conductivity type dopant on the first region and thesecond region of the substrate, and forming at least one dielectriclayer on the first material layer doped with the first conductivity typedopant in the first region and the second region, in accordance with oneembodiment of the present disclosure.

FIG. 14 is a perspective view of forming a block mask on the at leastone dielectric layer, and etching an exposed portion of the at least onedielectric layer and an underlying portion of the first material layerselective to the block mask to expose at least the second fin structurein the second region of the substrate, in accordance with one embodimentof the present disclosure.

FIG. 15 is a perspective view of removing the block mask and depositinga second material layer doped with the second conductivity type dopantin direct contact with a remaining portion of the at least onedielectric layer in the first region and in direct contact with thesecond fin structure in the second region of the substrate, inaccordance with one embodiment of the present disclosure.

FIG. 16 is a perspective view of driving the first conductivity dopantfrom the first material layer into the first fin structure, and drivingthe second conductivity type dopant from the second material layer intothe second fin structure, and forming raised source regions and raiseddrain regions, in accordance with one embodiment of the presentdisclosure.

FIG. 17 is a perspective view of defining semiconductor on insulator(SOI) portions, i.e., first and second SOI portions, from an SOI layerof a semiconductor on insulator (SOI) substrate, in accordance with oneembodiment of the present disclosure.

FIG. 18 is a perspective view of smoothing the nanowire portions of thefirst and second SOI portions of the substrate, in accordance with oneembodiment of the present disclosure.

FIG. 19 is a perspective view of forming a first and second gatestructures in direct contact with the first and second nanowire portionsof the substrate, in accordance with one embodiment of the presentdisclosure.

FIG. 20 is a perspective view of forming a spacer along the sidewalls ofthe first and second gate structures depicted in FIG. 19, in accordancewith one embodiment of the present disclosure.

FIG. 21 is a side cross-sectional view depicting depositing a firstmaterial layer doped with the first conductivity type dopant on thefirst and second SOI portions, and forming at least one dielectric layeron the first material layer, in accordance with one embodiment of thepresent disclosure.

FIG. 22 is a side cross-sectional view depicting forming a block mask onthe at least one dielectric layer over the first SOI portion, andetching an exposed portion of the at least one dielectric layer and anunderlying portion of the first material layer selective to the blockmask, in accordance with one embodiment of the present disclosure.

FIG. 23 is a side cross-sectional view depicting removing the block maskand depositing a second material layer doped with the secondconductivity type dopant in direct contact with a remaining portion ofthe at least one dielectric layer, and in direct contact with the secondnanowire portion, in accordance with one embodiment of the presentdisclosure.

FIG. 24 is a side cross-sectional view depicting driving the firstconductivity dopant from the first material layer into the firstnanowire portion, and driving the second conductivity type dopant fromthe second material layer into the second nanowire portion, inaccordance with one embodiment of the present disclosure.

DETAILED DESCRIPTION

Detailed embodiments of the present invention are disclosed herein;however, it is to be understood that the disclosed embodiments aremerely illustrative of the invention that may be embodied in variousforms. In addition, each of the examples given in connection with thevarious embodiments of the invention are intended to be illustrative,and not restrictive. Further, the figures are not necessarily to scale,some features may be exaggerated to show details of particularcomponents. Therefore, specific structural and functional detailsdisclosed herein are not to be interpreted as limiting, but merely as arepresentative basis for teaching one skilled in the art to variouslyemploy the present invention.

References in the specification to “one embodiment”, “an embodiment”,“an example embodiment”, etc., indicate that the embodiment describedmay include a particular feature, structure, or characteristic, butevery embodiment may not necessarily include the particular feature,structure, or characteristic. Moreover, such phrases are not necessarilyreferring to the same embodiment. Further, when a particular feature,structure, or characteristic is described in connection with anembodiment, it is submitted that it is within the knowledge of oneskilled in the art to affect such feature, structure, or characteristicin connection with other embodiments whether or not explicitlydescribed. For purposes of the description hereinafter, the terms“upper”, “lower”, “right”, “left”, “vertical”, “horizontal”, “top”,“bottom”, and derivatives thereof shall relate to the invention, as itis oriented in the drawing figures. The terms “overlying”, “atop”,“positioned on” or “positioned atop” means that a first element, such asa first structure, is present on a second element, such as a secondstructure, wherein intervening elements, such as an interface structure,e.g. interface layer, may be present between the first element and thesecond element. The term “direct contact” means that a first element,such as a first structure, and a second element, such as a secondstructure, are connected without any intermediary conducting, insulatingor semiconductor layers at the interface of the two elements.

The embodiments of the present disclosure relate to methods forproducing semiconductor devices in which a material layer that isdeposited over a gate structure and adjacent portions of the substrateis used to introduce a dopant for the source and drain extension regionswithout ion implantation. A semiconductor device is an intrinsicsemiconductor material that has been doped, that is, into which a dopingagent has been introduced, giving it different electrical propertiesthan the intrinsic semiconductor. Doping involves adding dopant atoms toan intrinsic semiconductor, which changes the electron and hole carrierconcentrations of the intrinsic semiconductor at thermal equilibrium.Dominant carrier concentration in an extrinsic semiconductor determinesthe conductivity type of the semiconductor. As used herein, the term“conductivity type” denotes a dopant region being p-type or n-type. Inone embodiment, introducing the dopant into the source and drainextension regions using the doped material layer in combination with adriving anneal avoids damaging the crystal structure of thesemiconductor material in which the source and drain extension regionsare positioned.

In one example, the crystal structure of the source and drain extensionregion that is provided in the present method and structure is a singlecrystal semiconductor material. A single crystal semiconductor materialis a crystalline solid in which atoms are arranged following a specificpattern throughout the entire piece of the material; i.e., a long-rangeorder exists throughout. In contrast, a polycrystalline material is amaterial in which a long-range order exists only within a portion of thegrains, wherein the grains are randomly connected to form a solid. In apolycrystalline material there is no preferential extension of thesingle-crystal within the grain in any direction. In contrast topolycrystalline and single crystal materials, an amorphous material is anon-crystalline solid with no periodicity and no long-range order atall.

The introduction of a dopant to the source and drain extension regionsby diffusing the dopant into an underlying semiconductor layer issuitable for forming single crystal source and drain extension regionsin planar semiconductor devices positioned on extremely thinsemiconductor on insulator (ETSOI) substrates. By “extremely thinsemiconductor on insulator” it is meant that the upper semiconductorlayer, which is present on a buried insulating layer, has a thickness of10 nm or less. It has been determined that the use of ion implantationto form source and drain extension regions disrupts the single crystalorientation of the semiconductor material, and when employed in ETSOIsubstrates impacts the entire depth of the crystal structure of theupper semiconductor so that there is no remaining single crystalmaterial that may be used in a regrowth step. Therefore, the damagecaused by the ion implantation results in an ETSOI layer having a highresistance, which results from the amorphous or polycrystalline sourceand drain extension regions. In one embodiment, the present methodavoids ion implantation of the source and drain extension regions.

FIGS. 1-6 depict one embodiment of a method for forming a planarsemiconductor device, such as a field effect transistor on a substrate.A planar semiconductor device is a semiconductor device in which thecurrent flow through the channel of the device is in a direction that isparallel to the upper surface of the substrate on which thesemiconductor device is formed. As used herein, the channel is theregion between the source and drain of a semiconductor device thatbecomes conductive when the semiconductor device is turned on. The drainis the doped region in semiconductor device located at the end of thechannel, in which carriers are flowing out of the semiconductor throughthe drain. The term source is a doped region in the semiconductordevice, in which majority carriers are flowing into the channel. In oneembodiment, the semiconductor device is a field effect transistor (FET).As used herein a “field effect transistor” is a transistor in whichoutput current, i.e., source-drain current, is controlled by the voltageapplied to a gate structure. A field effect transistor has threeterminals, i.e., gate structure, source and drain. The gate structure isa structure used to control output current (i.e., flow of carriers inthe channel) of a semiconducting device, such as a field effecttransistor, through electrical or magnetic fields. In one embodiment,the present disclosure avoids damaging the crystal structure of thesubstrate by forming a doped material layer on the upper semiconductorlayer, e.g., ETSOI layer, of the substrate after the gate structureshave been formed, and then diffusing the dopant from the doped materiallayer into the upper semiconductor layer, e.g., ETSOI layer, using ananneal process.

FIG. 1 depicts one embodiment of a substrate 5 having a first region 15and a second region 20, in which a first gate structure 35 is present inthe first region 15 and a second gate structure 40 is present in thesecond region 20. The substrate 5 may be a semiconductor on insulator(SOI) substrate. In the embodiments, in which the substrate 5 is an SOIsubstrate, the substrate 5 is typically composed of at least a firstsemiconductor layer 4 (hereafter referred to as an ETSOI layer 4)overlying a dielectric layer 3, wherein the ETSOI layer 4 has athickness T1 of less than 10 nm. A second semiconductor layer 2 may bepresent underlying the dielectric layer 3.

The ETSOI layer 4 may comprise any semiconducting material including,but not limited to: Si, strained Si, SiC, SiGe, SiGeC, Si alloys, Ge, Gealloys, GaAs, InAs, and InP, or any combination thereof. The ETSOI layer4 may be thinned to a desired thickness by planarization, grinding, wetetch, dry etch or any combination thereof. One method of thinning theETSOI layer 4 is to oxidize the Si by a thermal dry or wet oxidationprocess, and then wet etch the oxide layer using a hydrofluoric acidmixture. This process can be repeated to achieve the desired thickness.In one embodiment, the ETSOI layer 4 has a thickness ranging from 1.0 nmto 10.0 nm. In another embodiment, the ETSOI layer 4 has a thicknessranging from 1.0 nm to 5.0 nm. In a further embodiment, the ETSOI layer4 has a thickness ranging from 3.0 nm to 8.0 nm. The secondsemiconductor layer 2 may be a semiconducting material including, butnot limited to: Si, strained Si, SiC, SiGe, SiGeC, Si alloys, Ge, Gealloys, GaAs, InAs, InP as well as other III/V and II/VI compoundsemiconductors.

The dielectric layer 3 that may be present underlying the ETSOI layer 4and atop the second semiconductor layer 2 may be formed by implanting ahigh-energy dopant into the substrate 5 and then annealing the structureto form a buried oxide layer, i.e., dielectric layer 3. In anotherembodiment, the dielectric layer 3 may be deposited or grown prior tothe formation of the ETSOI layer 4. In yet another embodiment, thesubstrate 5 may be formed using wafer-bonding techniques, where a bondedwafer pair is formed utilizing glue, adhesive polymer, or directbonding.

In one embodiment, the substrate 5 includes a first region 15 and asecond region 20. The positioning of the first region 15 and the secondregion 20 may be determined by forming an isolation region 6 through theETSOI layer 4 and, in some embodiments, into contact with the dielectriclayer 3. In another embodiment, the isolation region 6 is a trenchfilled with an insulating material, such as an oxide, nitride, oroxynitride. In another embodiment, the isolation region 6 is a shallowtrench isolation (STI) region. In a further embodiment, the shallowtrench isolation region 6 may be formed by etching a trench in thesubstrate 5 utilizing a dry etching process, such as reactive-ionetching (RIE) or plasma etching. In a yet further embodiment, etching ofthe trench may include depositing an insulating material having acomposition different than the dielectric layer 3, such as a nitridewhen the dielectric layer 3 is an oxide. The trenches may optionally belined with a liner material, e.g., an oxide. In one embodiment, chemicalvapor deposition or another like deposition process may be used to fillthe trench with polysilicon or another like STI dielectric material,such as an oxide. A planarization process, such as chemical-mechanicalpolishing (CMP), may optionally be used to provide a planar structure.

Optionally, a plurality of well regions (not shown) may be locatedwithin the substrate 5 and separated by the isolation regions 6. In oneembodiment, the well regions correspond to the first and second regions15, 20, in which the isolation region 6 is present between the firstregion 15 and the second region 20. In one example, in which the firstregion 15 is processed to provide at least one n-type field effecttransistor (nFET), a first well region is present in the first region 15doped to a p-type conductivity. In one example, in which the secondregion 20 is processed to provide at least one p-type field effecttransistor (pFET), a second well region is present in the second region20 doped to an n-type conductivity. Alternatively, the regions 4 areessentially undoped or with a dopant concentration less than 1×10¹⁷atoms/cm³.

Still referring to FIG. 1, a first gate structure 35 is present in thefirst region 15 and a second gate structure 40 is present in the secondregion 20. Each of the first and second gate structures 35, 40 includeat least one gate dielectric 39, 43 and at least one gate conductor 37,42. In one example, the first gate structure 35 comprises a first gatedielectric 39 and a first gate conductor 37. In one example, the secondgate structure 40 comprises a second gate dielectric 43 and a secondgate conductor 42.

The first and second gate structures 35, 40 may be formed usingdeposition, photolithography and selective etch processes. A gate layerstack is formed in the first region 15 and second region 20 bydepositing at least one gate dielectric layer, i.e., material layers forthe first gate dielectric 39 and the second gate dielectric 43, on thesubstrate 5, and then depositing at least one gate conductor layer,i.e., material layers for the first gate conductor 37 and the secondgate conductor 42, on the at least one gate dielectric layer. The gatelayer stack is then patterned and etched to provide a first gatestructure 35 in the first region 15, and a second gate structure 40 inthe second region 20.

Specifically, a pattern is produced by applying a photoresist to thesurface to be etched, exposing the photoresist to a pattern ofradiation, and then developing the pattern into the photoresistutilizing a resist developer. Once the patterning of the photoresist iscompleted, the sections covered by the photoresist are protected whilethe exposed regions are removed using a selective etching process thatremoves the unprotected regions. In one embodiment, a hard mask(hereafter referred to as a dielectric cap 38) may be used to form thefirst and second gate structures 35, 40. The dielectric cap 38 may beformed by first depositing a dielectric hard mask material, like SiN orSiO₂, atop a layer of gate conductor material and then applying aphotoresist pattern to the hardmask material using a lithography processsteps. The photoresist pattern is then transferred into the hard maskmaterial using a dry etch process forming the dielectric cap 38. Nextthe photoresist pattern is removed and the dielectric cap 38 pattern istransferred into the gate conductor material during a selective etchingprocess. The dielectric cap 38 may be removed by a wet or dry etch priorto the silicidation process.

The first and second gate dielectrics 39, 43 may individually compriseseparate dielectric materials such as oxides, nitrides and oxynitridesof silicon that have a dielectric constant ranging from 3.9 to 10.0, asmeasured in a vacuum at room temperature. Alternatively, one or both ofthe first and second gate dielectric 39, 43 may be composed of a higherdielectric constant dielectric material having a dielectric constantranging from 10 to 100. Such higher dielectric constant dielectricmaterials may include, but are not limited to, hafnium oxides, hafniumsilicates, titanium oxides, barium-strontium-titantates (BSTs) andlead-zirconate-titanates (PZTs). The first and second gate dielectrics39, 43 may be formed using any of several deposition and growth methods,including but not limited to, thermal or plasma oxidation or nitridationmethods, chemical vapor deposition methods and physical vapor depositionmethods. The first and second gate dielectrics 39, 43 may be composed ofthe same material or different materials. Although the first and secondgate dielectrics 39, 43 are depicted in the supplied figures as eachbeing a single layer, embodiments have been contemplated in which thefirst and second gate dielectrics 39, 43 are each a multi-layeredstructure of conductive materials. In one embodiment, the first andsecond gate dielectrics 39, 43 have a thickness ranging from 10angstroms to 200 angstroms.

The first and second gate conductors 37, 42 may be composed ofconductive materials including, but not limited to, metals, metalalloys, metal nitrides and metal silicides, as well as laminates thereofand composites thereof. In one embodiment, the first and second gateconductors 37, 42 may be any conductive metal including, but not limitedto, W, Ni, Ti, Mo, Ta, Cu, Pt, Ag, Au, Ru, Ir, Rh, and Re, and alloysthat include at least one of the aforementioned conductive elementalmetals. The first and second gate conductors 37, 42 may also comprisedoped polysilicon and/or polysilicon-germanium alloy materials (i.e.,having a dopant concentration from 1E18 to 1E22 dopant atoms per cubiccentimeter) and polycide materials (doped polysilicon/metal silicidestack materials). The first and second gate conductors 37, 42 may becomposed of the same material or different materials. The first andsecond gate conductors 37, 42 may be formed using a deposition methodincluding, but not limited to, salicide methods, atomic layer depositionmethods, chemical vapor deposition methods and physical vapor depositionmethods, such as, but not limited to, evaporative methods and sputteringmethods. Although the first and second gate conductors 37, 42 aredepicted in the supplied figures as each being a single layer,embodiments have been contemplated in which the first and second gateconductors 37, 42 are each a multi-layered structure of conductivematerials.

The first and second gate structures 35, 40 may further comprisesidewalls spacers 11, 12. The first and second sidewall spacers 11, 12may be composed of dielectric materials. The first sidewall spacer 11and the second sidewall spacer 12 are typically formed by using ablanket layer deposition and anisotropic etchback method. In oneembodiment, the first sidewall spacer 11 and the second sidewall spacer12 are composed of silicon oxide and have a thickness ranging from 1 nmto 10 nm.

FIG. 2 depicts one embodiment of depositing a first material layer 7doped with the first conductivity type dopant on the first region 15 andthe second region 20 of the substrate 5. by doped it is meant that thefirst material layer contains n-type or p-type dopant. In oneembodiment, in which the semiconductor device being formed in the firstregion 15 of the substrate 5 is an p-type semiconductor device, i.e.,p-type field effect transistor (pFET), the first conductivity typedopant of the first material layer 7 is a p-type dopant. As used herein,“p-type” refers to the addition of impurities to an intrinsicsemiconductor that creates deficiencies of valence electrons. In asilicon-containing substrate, examples of p-type dopants include, butare not limited to, boron, aluminum, gallium and indium. The firstmaterial layer 7 may be composed of any material that can carry thefirst type dopant and is capable of diffusing the first type dopant intothe underlying ETSOI layer 4 of the substrate 5. In one embodiment,another critereon for selection of the material of the first materiallayer 7 is that it is capable of being removed selectively to theunderlying ETSOI layer 4. In one embodiment, the first material layer 7may be composed of a dielectric material, such as an oxide, nitride oroxynitride material. In another embodiment, the first material layer 7is a semiconductor material, such as polysilicon or single crystalsilicon. In one example, the first material layer 7 is composed of asilicate glass, such as a boron doped silicate glass.

In one embodiment, the first material layer 7 is deposited onto thefirst region 10 and the second region 15 of the substrate 5. The firstmaterial layer 7 may be deposited using chemical vapor deposition (CVD).Chemical vapor deposition (CVD) is a deposition process in which adeposited species is formed as a result of chemical reaction betweengaseous reactants at greater than room temperature (25° C. to 900° C.);wherein solid product of the reaction is deposited on the surface onwhich a film, coating, or layer of the solid product is to be formed.Variations of CVD processes include, but not limited to, AtmosphericPressure CVD (APCVD), Low Pressure CVD (LPCVD) and Plasma Enhanced CVD(EPCVD), Metal-Organic CVD (MOCVD) and combinations thereof may also beemployed. Other deposition methods that are suitable for depositing thefirst material layer 7 include, but are not limited to: spinning fromsolution, spraying from solution, chemical sputter deposition, reactivesputter deposition, ion-beam deposition, and evaporation. In oneembodiment, the first material layer 7 is deposited using a conformaldeposition process. The term “conformal” denotes a layer having athickness that does not deviate from greater than or less than 20% of anaverage value for the thickness of the layer. The thickness of the firstmaterial layer 7 may range from 1 nm to 25 nm. In one embodiment, thethickness of the first material layer 7 ranges from 5 nm to 10 nm.

In one embodiment, the first conductivity type dopant is introduced tothe first material layer 7 during the deposition process that forms thefirst material layer 7. In another embodiment, the first material layer7 is deposited on the first and second region 15, 20 of the substrate 5,and the first conductivity type dopant is then introduced to the firstmaterial layer 7 after its deposition using ion implantation. Theconcentration of the first conductivity type dopant in the firstmaterial layer 7 may range from 1×10¹⁹ atoms/cm³ to 3×10²² atoms/cm³. Inanother embodiment, the concentration of the first conductivity typedopant in the first material layer 7 may range from 1×10²¹ atoms/cm³ to1×10²² atoms/cm³. In yet another embodiment, the concentration of thefirst conductivity type dopant in the first material layer 7 may rangefrom 2×10²¹ atoms/cm³ to 5×10²¹ atoms/cm³.

FIG. 2 further depicts forming at least one dielectric layer 9 on thefirst material layer 7. In one embodiment, the at least one dielectriclayer 9 may be formed on the first material material layer 7 in both thefirst region 10 and the second region 20. The at least one dielectriclayer 9 may be formed by a thermal growth process such as, for example,oxidation, nitridation or oxynitridation. The at least one dielectriclayer 9 may also be formed by a deposition process such as, for example,chemical vapor deposition (CVD), plasma-assisted CVD, metal organicchemical vapor deposition (MOCVD), atomic layer deposition (ALD),evaporation, reactive sputtering, chemical solution deposition and otherlike deposition processes. In one embodiment, the at least onedielectric layer 9 is deposited using a conformal deposition process.The at least one dielectric layer 9 may be composed of any dielectricmaterial that can be etched selectively with respect to the underlyingfirst material layer 7. The at least one dielectric layer 9 may becomposed of an oxide, nitride or oxynitride material.

In one embodiment, the at least one dielectric layer 9 employed in thepresent disclosure includes, but is not limited to, an oxide, nitride,oxynitride and/or silicates including metal silicates, aluminates,titanates and nitrides. In one example, when the at least one dielectriclayer 9 is comprised of an oxide, the oxide may be selected from thegroup including, but not limited to, SiO₂, HfO₂, ZrO₂, Al₂O₃, TiO₂,La₂O₃, SrTiO₃, LaAlO₃, Y₂O₃ and mixture thereof. In another embodiment,the at least one dielectric layer 9 is composed of a nitride, such assilicon nitride. The physical thickness of the at least one dielectriclayer 9 may vary, but typically, the at least one dielectric layer 9 hasa thickness ranging from 1 nm to 10 nm. In another embodiment, the atleast one dielectric layer 9 has a thickness ranging from 1 nm to 3 nm.

FIG. 3 depicts one embodiment of forming a block mask 70 on the at leastone dielectric layer 9 in the first region 15, and etching an exposedportion of the at least one dielectric layer 9 and an underlying portionof the first material layer 7 selective to the block mask 70 to exposeat least the ETSOI layer 4 in the second region 20 of the substrate 5.In one embodiment, a block mask 70 is formed protecting the portion ofthe at least one dielectric layer 9 and the first material layer 7 thatare present in the first region 15 of the substrate 5 in which p-typesemiconductor devices, e.g., pFETs, are subsequently formed. The exposedportion of the at least one dielectric layer 9 and the first materiallayer 7 that is present in the second region 20 and is not protected bythe block mask 70 is subsequently removed.

The block mask 70 may comprise soft and/or hardmask materials and can beformed using deposition, photolithography and etching. In oneembodiment, the block mask 70 comprises a photoresist. A photoresistblock mask can be produced by applying a photoresist layer to thesurface to be etched, exposing the photoresist layer to a pattern ofradiation, and then developing the pattern into the photoresist layerutilizing a resist developer.

Alternatively, the block mask 70 can be a hardmask material. Hardmaskmaterials include dielectric systems that may be deposited by chemicalvapor deposition (CVD) and related methods. Typically, the hardmaskcomposition includes silicon oxides, silicon carbides, silicon nitrides,silicon carbonitrides, etc. Spin-on dielectrics may also be utilized asa hardmask material including, but not limited to: silsequioxanes,siloxanes, and boron phosphate silicate glass (BPSG). A block mask 70comprising a hardmask material may be formed by blanket depositing alayer of hardmask material, providing a patterned photoresist atop thelayer of hardmask material, and then etching the layer of hardmaskmaterial to provide a block mask 70 protecting the first region 15, inwhich etching comprises an etch chemistry having a high selectivity tothe patterned photoresist and the surface of the second region 20.

FIG. 3 also depicts removing the first material layer 7 and the at leastone dielectric layer 9 from the second region 20 of the substrate 5using a selective etch process. As used herein, the term “selective” inreference to a material removal process denotes that the rate ofmaterial removal for a first material is greater than the rate ofremoval for at least another material of the structure to which thematerial removal process is being applied. In one embodiment, theselective etch process may include an isotropic etch or an anisotropicetch. An anisotropic etch process is a material removal process in whichthe etch rate in the direction normal to the surface to be etched isgreater than in the direction parallel to the surface to be etched. Theanisotropic etch may include reactive-ion etching (RIE). Reactive ionetching (RIE) is a form of plasma etching in which during etching thesurface to be etched is placed on the RF powered electrode. Moreover,during RIE the surface to be etched takes on a potential thataccelerates the etching species extracted from a plasma toward thesurface, in which the chemical etching reaction is taking place in thedirection normal to the surface. Other examples of anisotropic etchingthat can be used at this point of the present invention include ion beametching, plasma etching or laser ablation. In contrast to anisotropicetching, isotropic etching is a form of etching that does not include apreferential direction. One example of an isotropic etch is wet etching.

In one embodiment, the selective etch process includes a first etchchemistry for removing the exposed portion of the at least onedielectric layer 9 selective to the underlying portion of the firstmaterial layer 7 and selective to the block mask 70. A second etchchemistry may then remove the exposed portion of the first materiallayer 7 selective to the underlying portion of the ETSOI layer 4 andselective to the block mask 70. The second etch chemistry is alsoselective to the second gate structure 40 and the sidewall spacers 12.

FIG. 4 depicts one embodiment of removing the block mask 70 anddepositing the second material layer 8 doped with the secondconductivity type dopant in direct contact with a remaining portion ofthe at least one dielectric layer 9 in the first region 15 and in directcontact with the semiconductor layer, i.e., ETSOI layer 4, in the secondregion 20 of the substrate 5. The second conductivity type dopant is anopposite conductivity type as the first conductivity type dopant. Forexample, when the first conductivity type dopant is p-type, the secondconductivity type dopant is n-type. The block mask 70 may be removed byselective etch processes, chemical strip methods, oxygen ashing orcombinations thereof.

In one embodiment, in which the semiconductor device being formed in thesecond region 20 of the substrate 5 is an n-type semiconductor device,i.e., n-type field effect transistor (pFET), the second conductivitytype dopant of the second material layer 8 is an n-type dopant. As usedherein, “n-type” refers to the addition of impurities that contributesfree electrons to an intrinsic semiconductor. In a silicon-containingsubstrate examples of n-type dopants, i.e., impurities, include but arenot limited to, antimony, arsenic and phosphorous.

The second material layer 8 may be composed of any material that cancarry the second type dopant and is capable of diffusing the second typedopant into the underlying ETSOI layer 4 of the substrate 5. In oneembodiment, another critereon for selection of the material of thesecond material layer 8 is that it is capable of being removedselectively to the underlying ETSOI layer 4. In one embodiment, thesecond material layer 8 may be composed of a dielectric material, suchas an oxide, nitride or oxynitride material. In another embodiment, thesecond material layer 8 is a semiconductor material, such as polysiliconor single crystal silicon. In one example, the second material layer 8is composed of a silicate glass, such as a boron doped silicate glass.

In one embodiment, the second material layer 8 is deposited onto thefirst region 10 and the second region 15 of the substrate 5. The secondmaterial layer 8 may be deposited using chemical vapor deposition (CVD)including, but not limited to, Atmospheric Pressure CVD (APCVD), LowPressure CVD (LPCVD) and Plasma Enhanced CVD (EPCVD), Metal-Organic CVD(MOCVD) and combinations thereof may also be employed. Other depositionmethods that are suitable for depositing the second material layer 8include, but are not limited to: spinning from solution, spraying fromsolution, chemical sputter deposition, reactive sputter deposition,ion-beam deposition, and evaporation. In one embodiment, the secondmaterial layer 8 is deposited using a conformal deposition process. Thethickness of the second material layer 8 may range from 1 nm to 25 nm.In one embodiment, the thickness of the second material layer 8 rangesfrom 5 nm to 10 nm.

In one embodiment, the second conductivity type dopant is introduced tothe second material layer 8 during the deposition process that forms thesecond material layer 8. In another embodiment, the second materiallayer 8 is deposited on the first and second region 15, 20 of thesubstrate 5, and the second conductivity type dopant is then introducedto the second material layer 8 after its deposition using ionimplantation. The concentration of the second conductivity type dopantin the second material layer 8 may range from 1×10¹⁹ atoms/cm³ to 3×10²²atoms/cm³. In another embodiment, the concentration of the secondconductivity type dopant in the second material layer 8 may range from1×10²¹ atoms/cm³ to 1×10²² atoms/cm³. In yet another embodiment, theconcentration of the second conductivity type dopant in the secondmaterial layer 8 may range from 2×10²¹ atoms/cm³ to 5×10²¹ atoms/cm³.

FIG. 5 depicts one embodiment of driving the first conductivity dopantfrom the first material layer 7 into the first region 15 of thesubstrate 5, and driving the second conductivity type dopant from thesecond material layer 8 into the second region 20 of the substrate 5. Inone embodiment, the dopant from the first material layer 7 and secondmaterial layer 8 is diffused into the ETSOI layer 4 by an annealingprocesses including, but not limited to, rapid thermal annealing,furnace annealing, flash lamp annealing or laser annealing. In oneembodiment, thermal annealing to diffuse the dopant from the secondmaterial layer 8 and the first material layer 7 into the underlyingETSOI layer 4 is conducted at a temperature ranging from 850° C. to1350° C.

In one embodiment, in which the first conductivity type dopant in thefirst material layer 7 is a p-type dopant, the source extension region13 and drain extension region 14 that are formed in the ETSOI layer 4 inthe first region 15 have a p-type conductivity. Typically, the dopantconcentration of the source extension region 13 and drain extensionregion 14 having the p-type conductivity ranges from 1×10¹⁹ atoms/cm³ to1×10²¹ atoms/cm³. In another embodiment, the source extension region 13and drain extension region 14 having the p-type conductivity ranges from4×10¹⁹ atoms/cm³ to 4×10²⁰ atoms/cm³.

In one embodiment, in which the first conductivity type dopant in thefirst material layer 7 is doped to an n-type conductivity, the sourceextension region 16 and drain extension region 17 that are formed in theETSOI layer 4 in the second region 20 have an n-type conductivity.Typically, the dopant concentration of the source extension region 16and drain extension region 17 having the n-type conductivity ranges from1×10¹⁹ atoms/cm³ to 1×10²¹ atoms/cm³. In another embodiment, the sourceextension region 16 and drain extension region 17 having the n-typeconductivity ranges from 4×10¹⁹ atoms/cm³ to 4×10²⁰ atoms/cm³.

Still referring to FIG. 5, the source extension regions 13, 16 and drainextension regions 14, 17 have a depth that typically, but notnecessarily always, extend the entire depth of the ETSOI layer 4.Therefore, the source extension regions 13, 16 and the drain extensionregions 14, 17 have a depth of less than 10 nm, typically being 3 nm to8 nm in depth, as measured from the upper surface of the ETSOI layer 4.Following the formation of the source and drain extension regions 13,16, the first material layer 7, the at least one dielectric layer 9 andthe second material layer 8 may be removed using an etch process thatremoves the material layers selective to the first and second gatestructure 35, 40, the ETSOI layer 4 and the isolation regions 6.

FIG. 6 depicts forming raised source and drain regions in the firstregion 15 and the second region 20 of the substrate 5. The term “raised”used to describe the raised source and drain regions 18, 19, 21 and 22mean that the semiconductor material of these portions of thesemiconductor device have an upper surface that is vertically offset andabove the upper surface of the ETSOI layer 4, in the channel region ofthe device is present. In one embodiment, the raised source regions 18,21 and the raised drain regions 19, 22 are formed on an upper surfacethe semiconductor layer, i.e., ETSOI layer 4, that contains the sourceand drain extension regions 13, 14, 16, 17, wherein the raised sourceregions 18, 21 and the raised drain regions 19, 22 are on opposing sidesof the first and second gate structure 35, 40.

In one embodiment, the raised source and drain regions 18, 19, 21 and 22is composed of an epitaxially formed material, and has a thicknessranging from 5 nm to 80 nm, as measured from the upper surface of theETSOI layer 4. In another embodiment, each of the raised source anddrain regions 18, 19, 21, 22 has a thickness ranging from 10 nm to 50nm, as measured from the upper surface of the ETSOI layer 4. In yetanother embodiment, the raised source and drain regions 18, 19, 21, 22have a thickness ranging from 10 nm to 20 nm, as measured from the uppersurface of the ETSOI layer 4. In a yet further embodiment, the thicknessof the raised source and drain regions 18, 19, 21, 22 is substantiallyequal to the thickness of the ETSOI layer 4.

The raised source and drain regions 18, 19, 21, 22 may be selectivelyformed in direct contact with the ETSOI layer 4. The raised source anddrain regions 18, 19, 21, 22 can be formed using an epitaxial growthprocess. As used herein, the terms “epitaxially formed”, “epitaxialgrowth” and/or “epitaxial deposition” mean the growth of a semiconductormaterial on a deposition surface of a semiconductor material, in whichthe semiconductor material being grown has the same crystallinecharacteristics as the semiconductor material of the deposition surface.When the chemical reactants are controlled and the system parameters setcorrectly, the depositing atoms arrive at the surface of the ETSOI layer4 with sufficient energy to move around on the surface and orientthemselves to the crystal arrangement of the atoms of the depositionsurface. Thus, an epitaxial film deposited on a {100} crystal surfacewill take on a {100} orientation. If, on the other hand, the wafersurface has an amorphous surface layer, possibly the result ofimplanting, the depositing atoms have no surface to align to, resultingin the formation of polysilicon instead of single crystal silicon.

The raised source and drain regions 18, 19, 21, 22 may be provided byselective growth of silicon. The silicon may be single crystal,polycrystalline or amorphous. The raised source and drain regions 18,19, 21, 22 may be epitaxial silicon. The raised source and drain regions18, 19, 21, 22 may also be provided by selective growth of germanium.The germanium may be single crystal, polycrystalline or amorphous. Inanother example, the raised source and drain regions 18, 19, 21, 22 maybe composed of SiGe.

A number of different sources may be used for the selective depositionof silicon. Silicon sources for growth of silicon (epitaxial orpoly-crystalline) include silicon tetrachloride, dichlorosilane(SiH₂Cl₂), and silane (SiH₄). The temperature for epitaxial silicondeposition typically ranges from 550° C. to 900° C. Higher temperaturetypically results in faster deposition; the faster deposition may resultin crystal defects and film cracking. In one embodiment, the raisedsource and drain regions 18, 19, 21, 22 each have a tapered portion thatextends from the first and second sidewall spacers 11, 12. Morespecifically, in this embodiment, the thickness of the tapered portionof the raised source and drain regions 18, 19, 21, 22 increases in thelateral direction away from the first and second sidewall spacers 11,12. Following the taper portion, the upper surface of the raised sourceand drain regions 18, 19, 21, 22 is substantially parallel to the uppersurface of the ETSOI layer 4. In one embodiment, another set of spacers24 is formed adjacent to the first and second sidewall spacers 11, 12prior to forming the raised source and drain regions 18, 19, 21, 22.

The raised source and drain regions 18, 19, 21, 22 are doped with adopant having a same conductivity as the underlying source extensionregions 13, 16 and the underlying drain extension regions 14, 17. Forexample, and in the embodiments in which the source extension regions 13and drain extension regions 14 that are present in the first region 15are doped to a p-type conductivity, the raised source regions 18 and theraised drain regions 19 that are present in the first region 15 aredoped to a p-type conductivity. In the embodiments in which the sourceextension regions 16 and the drain extension regions 17 that are presentin the second region 20 are doped to an n-type conductivity, the raisedsource regions 21 and the raised drain regions 22 that are present inthe second region 20 are doped to an n-type conductivity. The dopant maybe introduced in-situ during the epitaxial growth process that forms theraised source and drain regions 18, 19, 21, 22. In another embodiment,the dopant may be introduced using ion implantations following theepitaxial growth process that deposits the semiconductor material of theraised source and drain regions 18, 19, 21, 22. Resulting dopantconcentrations for the raised source and drain regions 18, 19, 21, 22may range from 2×10¹⁹ dopant atoms per cubic centimeter to 5×10²¹ dopantatoms per cubic centimeter.

FIG. 6 further depicts forming metal semiconductor alloy regions 23 onan upper surface of the raised source and drain regions 18, 19, 21, 22.In one embodiment, the metal semiconductor alloy 23 is a silicide.Silicide formation typically requires depositing a refractory metal suchas Ni or Ti onto the surface of a Si-containing material. Followingdeposition, the structure is then subjected to an annealing step usingconventional processes such as, but not limited to, rapid thermalannealing. During thermal annealing, the deposited metal reacts with Siforming a metal silicide.

FIG. 6 depicts one embodiment of a semiconductor device that may beformed using the above-described method. A p-type semiconductor device,such as a p-type field effect transistor, may be formed in the firstregion 15 of the substrate 5, and an n-type semiconductor device, suchas an n-type field effect transistor, may be formed in the second region20 of the substrate 5. Each of the semiconductor devices may include agate structure, i.e., first and second gate structures 35, 40, on afirst portion of a semiconductor layer, i.e., ETSOI layer 4, having athickness of less than 10 nm. In one embodiment, the source and drainregions, i.e., source extension regions 13, 16 and drain extensionregions 14, 17, are present in the ETSOI layer 4 on opposing sides ofthe first portion of the semiconductor layer that the gate structure ispresent on. The source extension regions 13, 16 and the drain extensionregions 14, 17 may extend to an entire thickness of the ETSOI layer 4.The crystal structure of the source extension regions 13, 16 and thedrain extension regions 14, 17 in the semiconductor layer aredamage-free. The term “damage-free” with reference to the sourceextension regions 13, 16 and the drain extension region 14, 17 that arepresent in the ETSOI layer 4 means that a single crystal latticestructure is present from the upper surface of the ETSOI layer 4 to thebase of the ETSOI layer 4 that is in contact with the buried insulatinglayer 3. In contrast to a damage-free crystal structure, source anddrain extension regions that are formed in an ETSOI layer by ionimplantation have a damaged region that may be present through at leasta portion of the thickness of the ETSOI layer. The damaged regiondisrupts the long range order of the crystalline structure of the singlecrystal lattice structure, i.e., the order and pattern in which theatoms of the material of the ETSOI layer are arranged.

Although, the above examples depict a complementary metal oxidesemiconductor (CMOS) device, i.e., a semiconductor device including bothp-type and n-type semiconductor devices, the first and second regions15, 20 of the substrate 5 may include semiconductor devices of the sameconductivity type.

Although, the above examples are depicted using an ETSOI substrate, theabove method is also applicable to semiconductor devices formed on athick SOI substrate (not shown) or a bulk-semiconductor substrate 50, asdepicted in FIGS. 8 and 9. The term of “thick SOI substrate” refers toan SOI substrate that has an SOI thickness greater than 10 nm. Thebulk-semiconductor substrate 50 may be a silicon-containing material.Illustrative examples of Si-containing materials suitable for thebulk-semiconductor substrate include, but are not limited to, Si, SiGe,SiGeC, SiC, polysilicon, i.e., polySi, epitaxial silicon, i.e., epi-Si,amorphous Si, i.e., α:Si, and multi-layers thereof. Although silicon isthe predominantly used semiconductor material in wafer fabrication,alternative semiconductor materials can be employed, such as, but notlimited to, germanium, gallium arsenide, gallium nitride, silicongermanium, cadmium telluride and zinc sellenide.

A process flow for forming a semiconductor device using abulk-semiconductor substrate 50 is illustrated in FIG. 7. It is notedthat the process flow depicted in FIG. 7 is for illustrative purposesonly, and that intermediate process steps that are not illustrated inFIG. 7 may be further incorporated into the process flow. Referring toFIGS. 7, 8 and 9, step 110 includes forming a first gate structure 35 ina first region 15 of a bulk semiconductor substrate 50 and a second gatestructure 40 in a second region of the bulk semiconductor substrate 50.It is noted that the details of this process step have been describedabove with reference to FIG. 1, with the exception that the substrate isa bulk-semiconductor substrate 50 instead of an ETSOI substrate.

Referring to FIGS. 7 and 9, in one embodiment, step 115 includes formingstrain inducing wells 55, 60 on opposing sides of the first and secondgate structure 35, 40. In one embodiment, tensile stress inducing wells55 are positioned adjacent to the second gate structure 40 to an n-typesemiconductor device, such as an n-type field effect transistor (nFET).The tensile stress inducing wells 55 may include silicon doped withcarbon (Si:C) or silicon germanium doped with carbon (SiGe:C). Thetensile stress inducing wells 55 comprise intrinsically tensile Si:C canbe epitaxially grown atop a recessed portion of the bulk-semiconductorsubstrate 50. The term “intrinsically tensile Si:C” denotes that theSi:C is under an internal tensile stress, in which the tensile stress isproduced by a lattice mismatch between the smaller lattice dimension ofthe Si:C and the larger lattice dimension of the layer on which the Si:Cis epitaxially grown. The tensile stress inducing wells produce atensile stress within the device channel to the n-type semiconductordevice that is present in the second region 20 of the bulk-semiconductorsubstrate 50. The carbon (C) content of the epitaxial grown Si:C rangesfrom 0.3% to 10%, by atomic weight %. In another embodiment, the carbon(C) content of the epitaxial grown Si:C may range from 1% to 2%.

In one embodiment, compressive stress inducing wells 60 are positionedadjacent the first gate structure 35 in the first region 15 of thebulk-semiconductor substrate 50. Compressive stress inducing wells 60that are formed of intrinsically compressive SiGe can be epitaxiallygrown atop a recessed portion of the bulk-semiconductor substrate 50.The term “intrinsically compressive layer” denotes that the SiGe isunder an intrinsic compressive stress (also referred to as an intrinsiccompressive stress), in which the compressive stress is produced by alattice mismatch between the larger lattice dimension of the SiGe andthe smaller lattice dimension of the layer on which the SiGe isepitaxially grown. The compressive stress inducing wells 60 produce acompressive stress in the device channel. The Ge content of theepitaxial grown SiGe may range from 5% to 80%, by atomic weight %. Inanother embodiment, the Ge content of the epitaxial grown SiGe may rangefrom 10% to 50%. Step 115 is an optional step that is employed in aprocess sequence to provide the final structure depicted in FIG. 9. Step115 may be omitted in a process sequence to provide the final structuredepicted in FIG. 8.

Referring to FIGS. 7, 8 and 9, step 120 includes depositing a firstmaterial layer doped with a first conductivity type dopant on the firstand second region 15, 20 of the bulk-semiconductor substrate 50, anddepositing at least one dielectric layer on the first material layer. Itis noted that the details of this process step have been described abovewith reference to FIG. 2, with the exception that the substrate is abulk-semiconductor substrate 50 instead of an ETSOI substrate.

Referring to FIGS. 7, 8 and 9, step 130 includes forming a block mask 70on the at least one dielectric layer in the first region 15, and etchingthe exposed portion of the at least one dielectric layer and theunderlying portion of the first material layer. It is noted that thedetails of this process step have been described above with reference toFIG. 3, with the exception that the substrate is a bulk-semiconductorsubstrate 50 instead of an ETSOI substrate.

Referring to FIGS. 7, 8 and 9, step 140 includes removing the block mask70, and depositing a second material layer 8 doped with a secondconductivity type dopant in direct contact with a remaining portion ofthe at least one dielectric layer 9 in the first region 15, and indirect contact with the bulk-semiconductor 50 in the second region 20.It is noted that the details of this process step have been describedabove with reference to FIG. 4, with the exception that the substrate isa bulk-semiconductor substrate 50 instead of an ETSOI substrate.

Referring to FIGS. 7, 8 and 9, step 150 includes driving the firstconductivity type dopant and the second conductivity type dopant fromthe first and second material layer 7, 8 into the bulk semiconductorsubstrate 50 to provide the source extension regions 13, 16 and drainextension regions 14, 17. The source extension regions 13, 16 and drainextension regions 14, 17 extend to a depth of 10 nm or less, as measuredfrom the upper surface of the bulk-semiconductor substrate 50. It isnoted that the details of this process step have been described abovewith reference to FIG. 5, with the exception that the substrate is abulk-semiconductor substrate 50 instead of an ETSOI substrate. Followingthe formation of the source and drain extension regions 13, 14, 16, 17,the first material layer 7, the at least one dielectric layer 9 and thesecond material layer 8 may be removed using an etch process thatremoves the material layers selective to the first and second gatestructure 35, 40, the ETSOI layer 4 and the isolation regions 6.

Referring to FIG. 7, step 160 includes forming raised source and drainregions on an upper surface of the bulk-semiconductor substrate 50 onopposing sides of the first and second gate structures 35, 40, andforming metal semiconductor alloy regions. It is noted that the detailsof this process step have been described above with reference to FIG. 6,with the exception that the substrate is a bulk-semiconductor substrate50. It is noted that step 160 is optional.

FIGS. 8 and 9 depict some embodiments of a semiconductor device formedon a bulk-semiconductor semiconductor substrate 50 using the presentmethod. Similar to the semiconductor device depicted in FIG. 6, thecrystal structure of the source extension regions 13, 16 and drainextension regions 14, 17 that are formed in the bulk semiconductorsubstrate 50 is damage-free. The term “damage-free” means that thesingle crystal lattice structure of the source and drain extensionregions 13, 16, 14, 17 is substantially the same as the single crystallattice structure of the base material of the bulk semiconductorsubstrate 50 in which the source and drain extension regions 13, 16, 14,17 are not present.

In another embodiment, a finFET semiconductor device is formed by amethod that employs at least one material layer carrying a dopant tointroduce the dopant to the source and drain regions of the devicewithout ion implantation. A finFET is a semiconductor device thatincludes a fin structure. The fin structure is the body of asemiconductor device, in which the gate structure is positioned aroundthe fin structure such that charge flows down the channel on the twosidewalls of the fin structure and optionally along the top surface ofthe fin structure. In some embodiments, a material layer carrying ann-type or p-type dopant is utilized to introduce the dopant for thesource and drain extension regions into the fin structure.

FIGS. 10-16 depict one embodiment of a method of fabricating a finFETsemiconductor device having a fin structure 200 with a width W1 of lessthan 10 nm, in which the method does not use ion implantation to providethe source and drain extension regions in the fin structure of thedevice. FinFET formation typically requires ion implantation to formsource and drain extension regions. Ion implantation typically tends toamorphize the entire fin structure and generates implant-relateddefects. It is difficult to recrystallize the amorphous semiconductorand to eliminate implant defects during the subsequent low thermalbudget anneal process that are typically utilized in finFETmanufacturing. In one embodiment, the method disclosed herein overcomesthe disadvantages that result from ion implantation by forming thesource and drain extension regions in the fin structure using andielectric material layer carrying the dopant for the extension sourceand drain regions followed by an annealing process, wherein theannealing process drives the dopant from the doped dielectric materiallayer into the fin structure to form extension source and drain regions.

FIG. 10 depicts an initial structure used in one embodiment of a methodfor forming a finFET device. The initial structure may include a firstfin structure 201 in a first region of the substrate, and a second finstructure 202 in a second region of the substrate. The first finstructure 201 that is present in the first region of the substrate maybe subsequently processed to provide a p-type finFET. The second finstructure 202 that is present in the second region of the substrate maybe subsequently processed to provide an n-type finFET. The first andsecond fin structures 201, 202 may be present atop a dielectric layer203. In one embodiment, a dielectric fin cap 236 may be present on eachof the first fin structure 201 and the second fin structure 202. In oneembodiment, the fin structures 201, 202 and the dielectric layer 203 maybe provided from an SOI substrate, in which the top semiconductor layerof the SOI substrate provides the first and second fin structure 201,202. The SOI substrate typically includes a bottom semiconductor layer204 and a top semiconductor layer (hereafter referred to as an SOIlayer) that are electrically isolated from each other by a buriedinsulating layer (hereafter referred to as a dielectric layer 204). TheSOI layer and the bottom semiconductor layer 204 may comprise at leastone of Si, Ge alloys, SiGe, GaAs, InAs, InP, SiCGe, SiC as well as otherIII/V or II/VI compound semiconductors. The SOI layer and bottomsemiconductor layer 204 may comprise the same or different materials.

The dielectric layer 203 separating the SOI layer 200 and the bottomsemiconductor layer 100 may be a crystalline or non-crystalline oxide,nitride, oxynitride, or any other insulating material. The SOI substrateemployed in the present invention may be formed utilizing a layertransfer process including a bonding step. Alternatively, animplantation process such as SIMOX (Separation by IMplantation ofOXygen) can be used in forming the SOI substrate.

The thickness of the various layers of the SOI substrate may varydepending on the technique used in forming the same. In one embodiment,the SOI layer has a thickness ranging from 3 nm to 100 nm, thedielectric layer 203 (also referred to as buried dielectric layer) has athickness ranging from 10 nm to 150 nm, and the thickness of the bottomsemiconductor layer 204 of the SOI substrate may range from 10 nm to 500nm.

It is noted that although an SOI substrate is depicted and described inthe following discussion, embodiments of the present invention arecontemplated that utilize a bulk semiconductor substrate. In one exampleof the present invention, in which a bulk semiconductor substrate isused, the bulk semiconductor substrate comprises at least one of Si, Gealloys, SiGe, GaAs, InAs, InP, SiCGe, SiC as well as other III/V orII/VI compound semiconductors.

In one embodiment, prior to etching the SOI substrate to provide thefirst and second fin structures 201, 202, a layer of the dielectricmaterial that provides the dielectric fin cap 236 is deposited atop theSOI substrate. The dielectric fin cap 236 may be composed of a nitride,oxide, oxynitride material, and/or any other suitable dielectric layer.The dielectric fin cap 236 may comprise a single layer of dielectricmaterial or multiple layers of dielectric materials. The dielectriclayer can be formed by a deposition process, such as chemical vapordeposition (CVD) and/or atomic layer deposition (ALD). Alternatively,the dielectric fin cap 236 may be formed using a growth process, such asthermal oxidation or thermal nitridation. The dielectric fin cap 236 mayhave a thickness ranging from 1 nm to 100 nm. In one embodiment, thedielectric fin cap 236 is composed of an oxide, such as SiO₂, that isformed by chemical vapor deposition to a thickness on the order of 25 nmto 50 nm.

In one embodiment, following the formation of the layer of dielectricmaterial that provides the dielectric fin cap 236, a photolithographyand etch process sequence applied to the dielectric fin cap 236 and theSOI substrate may provide the initial structure that is depicted in FIG.5. Specifically, and in one example, a photoresist mask is formedoverlying the layer of the dielectric material that provides dielectricfin cap 236 and is present overlying the SOI layer of the substrate, inwhich the portion of the dielectric material that is underlying thephotoresist mask provides the dielectric fin cap 236, and the portion ofthe SOI layer that is underlying the photoresist mask provides the firstand second fin structures 201, 202. The exposed portions of thedielectric material and the SOI substrate, which are not protected bythe photoresist mask, are removed using a selective etch process. Toprovide the photoresist mask, a photoresist layer is first positioned onthe layer of the dielectric material that provides dielectric fin cap236. The photoresist layer may be provided by a blanket layer ofphotoresist material that is formed utilizing a deposition process suchas, for example, CVD, PECVD, evaporation or spin-on coating. The blanketlayer of photoresist material is then patterned to provide thephotoresist mask utilizing a lithographic process that may includeexposing the photoresist material to a pattern of radiation anddeveloping the exposed photoresist material utilizing a resistdeveloper.

Following the formation of the photoresist mask, an etching process mayremove the unprotected portions of the dielectric material that providesthe dielectric fin cap 236 followed by removing the unprotected portionof the SOI layer selective to the underlying buried insulating layer,i.e., dielectric layer 203. For example, the transferring of the patternprovided by the photoresist into the underlying structures may includean anisotropic etch. The anisotropic etch may include reactive-ionetching (RIE). Other examples of anisotropic etching that can be used atthis point of the present invention include ion beam etching, plasmaetching or laser ablation.

Each of the first and second fin structures 201, 202 may have a heightH₁ ranging from 5 nm to 200 nm. In one embodiment, each of the first andsecond fin structures 201, 202 have a height H₁ ranging from 10 nm to100 nm. In another embodiment, each of the first and second finstructures 201, 202 have a height H₁ ranging from 20 nm to 50 nm. In oneembodiment, the first and second fin structures 201, 202 each have awidth W₁ of less than 10 nm. In another embodiment, the first and secondfin structures 201, 202 each have a width W₁ ranging from 3 nm to 8 nm.

FIG. 11 depicts forming a gate structure 235 on the first and second finstructures 201, 202, and the dielectric fin cap 236. In one embodiment,the gate structure 235 includes a gate dielectric 237 in contact with atleast the first and second fin structures 201, 202, a gate conductor 238on the gate dielectric 237, and a gate dielectric cap 239 the gateconductor 238. The gate structure 235 may be formed by forming blanketmaterial layers for the gate dielectric 237, gate conductor 238, andgate dielectric cap 239 to provide a gate stack, and patterning andetching the gate stack to provide the gate structure 235. The patternedgate region 235 is formed utilizing photolithography and etch processsteps.

The gate dielectric 237 is typically positioned on at least a portion ofthe sidewalls of the first and second fin structures 201, 202. The gatedielectric 237 may be formed by a thermal growth process such as, forexample, oxidation, nitridation or oxynitridation. The gate dielectric237 may also be formed by a deposition process such as, for example,chemical vapor deposition (CVD), plasma-assisted CVD, metal organicchemical vapor deposition (MOCVD), atomic layer deposition (ALD),evaporation, reactive sputtering, chemical solution deposition and otherlike deposition processes. In one embodiment, the gate dielectric 90 isdeposited using a conformal deposition process.

The gate dielectric 237 may be comprised of an insulating materialhaving a dielectric constant of 4.0 or greater. In another embodiment,the gate dielectric 237 is comprised of an insulating material having adielectric constant greater than 7.0. The dielectric constants mentionedherein are relative to a vacuum at room temperature. In one embodiment,the gate dielectric 237 employed in the present invention includes, butis not limited to: an oxide, nitride, oxynitride and/or silicatesincluding metal silicates, aluminates, titanates and nitrides. In oneexample, when the gate dielectric 237 is comprised of an oxide, theoxide may be selected from the group including, but not limited to,SiO₂, HfO₂, ZrO₂, Al₂O₃, TiO₂, La₂O₃, SrTiO₃, LaAlO₃, Y₂O₃ and mixturethereof. The physical thickness of the gate dielectric 237 may vary, buttypically, the gate dielectric 237 has a thickness ranging from 1 nm to10 nm. In another embodiment, the gate dielectric 237 has a thicknessranging from 1 nm to 3 nm.

After forming the gate dielectric 237, the gate conductor 238 of thegate structure 235 is formed on the gate dielectric 237 utilizing adeposition process, such as physical vapor deposition (PVD), CVD orevaporation. The gate conductor 238 may be composed of polysilicon,SiGe, a silicide, a metal or a metal-silicon-nitride, such as Ta—Si—N.Examples of metals that can be used as the gate conductor 80 include,but are not limited to: Al, W, Cu, Ti or other like conductive metals.In one embodiment, the gate conductor 238 comprises Ti, Zr, Hf, V, Nb,Ta, TiN, TaN or a combination thereof. The gate conductor 238 may bedoped or undoped. The physical thickness of the gate conductor 238 mayrange from 1 nm to 10 nm. In another embodiment, the gate conductor 238has a thickness ranging from 1 nm to 3 nm.

The gate dielectric cap 239 may be composed of a nitride, oxide,oxynitride material, and/or any other suitable dielectric layer. Thegate dielectric cap 239 may comprise a single layer of dielectricmaterial or multiple layers of dielectric materials. The dielectriclayer can be formed by a deposition process, such as chemical vapordeposition (CVD) and/or atomic layer deposition (ALD). Alternatively,the gate dielectric cap 239 may be formed using a growth process, suchas thermal oxidation or thermal nitridation. The gate dielectric cap 239may have a thickness ranging from 1 nm to 100 nm. In one embodiment, thegate dielectric cap 239 is composed of a nitride, such as SiN, that isformed by chemical vapor deposition to a thickness on the order of 25 nmto 50 nm.

FIG. 12 depicts forming a first spacer 211 in direct contact with thegate structure 235. The first spacer 211 may be formed by depositing aconformal layer of dielectric material, such as oxides, nitrides oroxynitrides, and then etching the deposited layer. In one embodiment,the etching process is an anisotropic etching process, such as reactiveion etch. The first spacer 211 may have a width ranging from 1 nm to 10nm, typically ranging from 1 nm to 5 nm.

FIG. 13 depicts one embodiment of depositing a first material layer 207doped with the first conductivity type dopant on the first region andthe second region of the substrate, and forming at least one dielectriclayer 208 on the first material layer 207. In one embodiment, at least aportion of the first material layer 207 is in direct contact with theexposed portions of the first and second fin structures 201, 202.

In one embodiment, in which the semiconductor device being formed in thefirst region of the substrate is a p-type finFET, the first conductivitytype dopant of the first material layer 207 is a p-type dopant. Thefirst material layer 207 may be composed of any material that can carrythe first type dopant and is capable of diffusing the first type dopantinto the underlying first fin structure 201. In one embodiment, anothercritereon for selection of the material of the first material layer 207is that it is capable of being removed selectively to the underlyingfirst and second fin structures 201, 202. In another embodiment, thefirst material layer 207 may be composed of a dielectric material, suchas an oxide, nitride or oxynitride material. In one example, the firstmaterial layer 207 is composed of a silicate glass, such as an borondoped silicate glass.

In one embodiment, the first material layer 207 is deposited onto thefirst region and the second region of the substrate. The first materiallayer 207 may be deposited using chemical vapor deposition (CVD).Variations of CVD processes that are suitable for depositing the firstmaterial layer 207 include, but not limited to, Atmospheric Pressure CVD(APCVD), Low Pressure CVD (LPCVD) and Plasma Enhanced CVD (EPCVD),Metal-Organic CVD (MOCVD) and combinations thereof may also be employed.Other deposition methods that are suitable for depositing the firstmaterial layer 207 include, but are not limited to: spinning fromsolution, spraying from solution, chemical sputter deposition, reactivesputter deposition, ion-beam deposition, and evaporation. In oneembodiment, the first material layer 207 is deposited using a conformaldeposition process. The thickness of the first material layer 7 mayrange from 1 nm to 25 nm. In one embodiment, the thickness of the firstmaterial layer 7 ranges from 5 nm to 10 nm.

In one embodiment, the first conductivity type dopant is introduced tothe first material layer 207 during the deposition process that formsthe first material layer 207. In another embodiment, the first materiallayer 207 is deposited on the first and second region of the substrate,and the first conductivity type dopant is then introduced to the firstmaterial layer 207 after its deposition using ion implantation. Theconcentration of the first conductivity type dopant in the firstmaterial layer 207 may range from 1×10¹⁹ atoms/cm³ to 3×10²² atoms/cm³.In another embodiment, the concentration of the first conductivity typedopant in the first material layer 207 may range from 1×10²¹ atoms/cm³to 1×10²² atoms/cm³. In yet another embodiment, the concentration of thefirst conductivity type dopant in the first material layer 207 may rangefrom 2×10²¹ atoms/cm³ to 5×10²¹ atoms/cm³.

FIG. 13 further depicts forming at least one dielectric layer 209 on thefirst material layer 207. In one embodiment, the at least one dielectriclayer 209 may be formed on the first material material layer 207 in boththe first region and the second region. The at least one dielectriclayer 209 may be formed by a thermal growth process such as, forexample, oxidation, nitridation or oxynitridation. The at least onedielectric layer 209 may also be formed by a deposition process such as,for example, chemical vapor deposition (CVD), plasma-assisted CVD, metalorganic chemical vapor deposition (MOCVD), atomic layer deposition(ALD), evaporation, reactive sputtering, chemical solution depositionand other like deposition processes. In one embodiment, the at least onedielectric layer 209 is deposited using a conformal deposition process.The at least one dielectric layer 209 may be composed of any dielectricmaterial that can be etched selectively with respect to the underlyingfirst material layer 207. The at least one dielectric layer 209 may becomposed of an oxide, nitride or oxynitride material.

In one embodiment, the at least one dielectric layer 209 employed in thepresent disclosure includes, but is not limited to: an oxide, nitride,oxynitride and/or silicates including metal silicates, aluminates,titanates and nitrides. In one example, when the at least one dielectriclayer 9 is comprised of an oxide, the oxide may be selected from thegroup including, but not limited to: SiO₂, HfO₂, ZrO₂, Al₂O₃, TiO₂,La₂O₃, SrTiO₃, LaAlO₃, Y₂O₃ and mixture thereof. In another embodiment,the at least one dielectric layer 209 is composed of a nitride, such assilicon nitride. The physical thickness of the at least one dielectriclayer 209 may vary, but typically, the at least one dielectric layer 209has a thickness from 1 nm to 10 nm. In another embodiment, the at leastone dielectric layer 209 has a thickness from 1 nm to 3 nm.

FIG. 14 depicts one embodiment of forming a block mask 270 on the atleast one dielectric layer 209 in the first region, and etching anexposed portion of the at least one dielectric layer 209 and anunderlying portion of the first material layer 207 selective to theblock mask 270 to expose at least the second fin structure 202 and thefin cap dielectric 236 that is overlying the second fin structure 202 inthe second region of the substrate. In one embodiment, a block mask 270is formed protecting the portion of the at least one dielectric layer209 and the first material layer 207 that are present in the firstregion of the substrate in which p-type semiconductor devices, e.g.,pFETs, are subsequently formed. The exposed portion of the at least onedielectric layer 209 and the first material layer 207 that is present inthe second region and is not protected by the block mask 270 is removed.

The block mask 270 may comprise soft and/or hardmask materials and canbe formed using deposition, photolithography and etching. In oneembodiment, the block mask 270 comprises a photoresist. A photoresistblock mask 270 can be produced by applying a photoresist layer to thesurface of the substrate, exposing the photoresist layer to a pattern ofradiation, and then developing the pattern into the photoresist layerutilizing a resist developer.

In one embodiment, a selective etch process of a first etch chemistryremoves the exposed portion of the at least one dielectric layer 209selective to the underlying portion of the first material layer 207 andselective to the block mask 270. A second etch chemistry may then removethe exposed portion of the first material layer 207 selective to the fincap dielectric 236 that is overlying the second fin structure 202.

FIG. 15 depicts one embodiment of removing the block mask 270 anddepositing a second material layer 208 doped with the secondconductivity type dopant in direct contact with a remaining portion ofthe at least one dielectric layer 209 in the first region of thesubstrate and in direct contact with the second fin structure 202 andthe fin cap dielectric 236 that is overlying the second fin structure202 in the second region of the substrate. The second conductivity typedopant is an opposite conductivity type as the first conductivity typedopant. For example, when the first conductivity type dopant is p-type,the second conductivity type dopant is n-type. The block mask 270 may beremoved by selective etch processes, chemical strip methods, oxygenashing or combinations thereof.

In one embodiment, in which the semiconductor device being formed in thesecond region of the substrate is an n-type finFET, the secondconductivity type dopant of the second material layer 208 is an n-typedopant. As used herein, “n-type” refers to the addition of impuritiesthat contributes free electrons to an intrinsic semiconductor. In asilicon-containing substrate examples of n-type dopants, i.e.,impurities, include but are not limited to antimony, arsenic andphosphorous. The second material layer 208 may be composed of anymaterial that can carry the second type dopant and is capable ofdiffusing the second type dopant into the second fin structure 202. Inone embodiment, the second material layer 208 may be composed of adielectric material, such as an oxide, nitride or oxynitride material.In one example, the second material layer 208 is composed of a silicateglass, such as a boron doped silicate glass.

The second material layer 208 may be deposited using chemical vapordeposition (CVD) including, but not limited to, Atmospheric Pressure CVD(APCVD), Low Pressure CVD (LPCVD) and Plasma Enhanced CVD (EPCVD),Metal-Organic CVD (MOCVD) and combinations thereof may also be employed.Other deposition methods that are suitable for depositing the secondmaterial layer 208 include, but are not limited to: spinning fromsolution, spraying from solution, chemical sputter deposition, reactivesputter deposition, ion-beam deposition, and evaporation. In oneembodiment, the second material layer 208 is deposited using a conformaldeposition process. The thickness of the second material layer 208 mayrange from 1 nm to 25 nm. In one embodiment, the thickness of the secondmaterial layer 208 ranges from 5 nm to 10 nm.

In one embodiment, the second conductivity type dopant is introduced tothe second material layer 208 during the deposition process that formsthe second material layer 208. In another embodiment, the secondmaterial layer 208 is deposited on the first and second region of thesubstrate, and the second conductivity type dopant is then introduced tothe second material layer 208 after its deposition using ionimplantation. The concentration of the second conductivity type dopantin the second material layer 208 may range from 1×10¹⁹ atoms/cm³ to5×10²² atoms/cm³. In another embodiment, the concentration of the secondconductivity type dopant in the second material layer 208 may range from1×10²⁰ atoms/cm³ to 1×10²² atoms/cm³. In yet another embodiment, theconcentration of the second conductivity type dopant in the secondmaterial layer 208 may range from 2×10²¹ atoms/cm³ to 5×10²¹ atoms/cm³.

FIG. 16 depicts one embodiment of driving the first conductivity dopantfrom the first material layer 207 into the first fin structure 201, anddriving the second conductivity type dopant from the second materiallayer 208 into the second fin structure 202. In one embodiment, thedopant from the first material layer 207 and second material layer 208is diffused into the first fin structure 201 and the second finstructure 202 by an annealing processes including, but not limited to,rapid thermal annealing, furnace annealing, flash lamp annealing orlaser annealing. In one embodiment, thermal annealing to diffuse thedopant from the second material layer 208 and the first material layer207 into the first fin structure 201 and the second fin structure 202 isconducted at a temperature ranging from 850° C. to 1350° C.

In one embodiment, in which the first conductivity type dopant in thefirst material layer 207 is a p-type dopant, the concentration of thep-type dopant of that diffuses into the first fin structure 201 rangesfrom 1×10¹⁹ atoms/cm³ to 1×10²¹ atoms/cm³. In another embodiment, theconcentration of the p-type dopant that diffuses to the first finstructure 201 ranges from 4×10¹⁹ atoms/cm³ to 4×10²⁰ atoms/cm³.

In one embodiment, in which the second conductivity type dopant in thesecond material layer 208 is doped to an n-type conductivity, theconcentration of the n-type conductivity dopant that diffuses into thesecond fin structure 202 ranges from 1×10¹⁹ atoms/cm³ to 1×10²¹atoms/cm³. In another embodiment, the concentration of the n-typeconductivity dopant that diffuses to the second fin structure 202 rangesfrom 4×10¹⁹ atoms/cm³ to 4×10²⁰ atoms/cm³.

FIG. 16 further depicts removing the first material layer 207, the atleast one dielectric layer 209 and the second material layer 208 usingan etch process that is selective to at least the dielectric cap layer236, the first and second fin structures 201, 202, and the buriedinsulating layer, i.e., dielectric layer 203.

FIG. 16 also depicts one embodiment of forming first source and drainsemiconductor material 210 on the sidewalls of the first fin structure201, and forming second source and drain semiconductor material 212 onthe sidewall of the second fin structure 202. In one embodiment, thefirst source and drain semiconductor material 210 and the second sourceand drain semiconductor material 212 is formed using an epitaxial growthprocess. For example, the first and second source and drainsemiconductor materials 210, 212 may be composed of epitaxial silicon. Anumber of different sources may be used for the deposition of epitaxialsilicon. Silicon sources for epitaxial growth include silicontetrachloride, dichlorosilane (SiH₂Cl₂), and silane (SiH₄).

In one embodiment, the first source and drain semiconductor material 210may be provided by selective-epitaxial growth of SiGe. The Ge content ofthe epitaxial grown SiGe may range from 5% to 50%, by atomic weight %.In another embodiment, the Ge content of the epitaxial grown SiGe mayrange from 10% to 20%. In one embodiment, the epitaxial grown SiGeproduces a compressive strain in the portion of the first fin structure201, in which the channel of a semiconductor device, such as a p-typeconductivity finFET, is subsequently formed.

In one embodiment, the second source and drain semiconductor material212 may be provided by selective epitaxial growth of Si:C, i.e., silicondoped with carbon. In one embodiment, the C content of the epitaxialgrown Si:C ranges from 1% to 5%. In another embodiment, the C content ofthe epitaxial grown Si:C ranges from 1% to 2.5%. In one embodiment, theepitaxial grown Si:C produces a tensile strain in the portion of thesecond fin structure 202, in which the channel of a semiconductordevice, such as an n-type conductivity finFET, is subsequently formed.

In one embodiment, the dopant for the first and second source and drainsemiconductor materials 210, 212 may be introduced during the epitaxialgrowth process that produces the first and second source and drainsemiconductor materials 210, 212. In some embodiments, the dopant forthe first and second source and drain semiconductor material 210, 212may be implanted after the epitaxial growth process using ionimplantation.

In one embodiment, in which the first source and drain semiconductormaterial 210 provides the source and drain regions of a p-type finFETdevice, the first source and drain semiconductor material 210 may bedoped with elements from group III of the Periodic Table of Elements. Inone embodiment, the group III element is boron, aluminum, gallium orindium. In one example, in which the first source and drainsemiconductor material 210 is doped to provide a p-type conductivity,the dopant may be boron present in a concentration ranging from 1×10¹⁵atoms/cm³ to 5×10¹⁵ atoms/cm³. In one example, source and drainsemiconductor material 210 is composed of SiGe and is doped with boronto provide the raised source and drain regions of a p-type conductivityfinFET.

In one embodiment, in which the second source and drain semiconductormaterial 212 provides the source and drain regions of an n-type finFETdevice, the second source and drain semiconductor material 212 may bedoped with elements from group V of the Periodic Table of Elements. Inone embodiment, the group V element is phosphorus, antimony or arsenic.In one example, the dopant concentration of the second source and drainsemiconductor material 212 ranges from 5×10¹⁹ atoms/cm³ to 5×10²⁰atoms/cm³. In another embodiment, the second source and drainsemiconductor material 212 has a dopant concentration ranging from7×10¹⁹ atoms/cm³ to 2×10²⁰ atoms/cm³. Referring to FIGS. 10-16, theabove process may provide a finFET semiconductor device that includesfin structures 201, 202 having a width W1 of less than 10.0 nm. Thedopant from the first and second material layer 207, 208 diffuse throughthe entire width of the first and second fin structure 201, 202. In oneembodiment, the crystal structure of the dopant regions in the first andsecond fin structure 201, 202 is damage-free. The term “damage-free”means that a single crystal lattice structure is present across theentire width of the first and second fin structure 201, 202. In contrastto a damage-free crystal structure, dopant regions that are formed inthe first and second fin structures 201, 202 by ion implantation have adamaged region that may be present through at least a portion of thewidth of the fin structure. The damaged region disrupts the long rangeorder of the crystalline structure of the single crystal latticestructure, i.e., the order and pattern in which the atoms of thematerial of the fin structure are arranged. The present methodsubstantially eliminates the presence of damaged regions in the firstand second fin structures 201, 202.

FIGS. 17-24 depict one embodiment of a method of fabricating a nanowiresemiconductor device that does not use ion implantation to provide thesource and drain extension regions of the device. Semiconductor devicescomposed of nanowires typically require ion implantation to form thesource and drain extension regions. Ion implantation typically tends toamorphize the entire nanowire structure and generates implant-relateddefects. It is difficult to recrystallize the amorphous semiconductorand to eliminate implant defects during the subsequent low thermalbudget anneal process that are typically utilized in semiconductordevice manufacturing. In one embodiment, the method disclosed hereinovercomes the disadvantages that result from ion implantation by formingthe source and drain extension regions in the nanowire structure usingan dielectric material layer carrying the dopant for the extensionsource and drain regions followed by an annealing process, wherein theannealing process drives the dopant from the doped dielectric materiallayer into the nanowire structure to form extension source and drainregions.

Referring to FIG. 17, and in one embodiment, semiconductor on insulator(SOI) portions 301, 302 are defined, i.e., patterned and etched, fromthe SOI layer of a semiconductor on insulator (SOI) substrate. Thesemiconductor on insulator (SOI) substrate includes a firstsemiconductor layer that provides the semiconductor on insulator (SOI)portions 301, 302, a dielectric layer 303 that is underlying the firstsemiconductor layer, and a second semiconductor layer 300 that is underthe dielectric layer 303. In some embodiments, when the firstsemiconductor layer is less than 10 nm thick, the SOI substrate may bereferred to as an extremely thin semiconductor on insulator (ETSOI)substrate. The SOI and ETSOI substrates that are described above in theembodiments of the invention depicted in FIGS. 1-16 are suitable forproviding the first and second SOI portions 301, 302.

The first SOI portion 301 may be subsequently processed to provide ap-type semiconductor device in which the channel of the device ispositioned in a first nanowire portion 309A. The second SOI portion 302may be subsequently processed to provide a p-type semiconductor devicein which the channel of the device is positioned in a second nanowireportion 309B. Each of the SOI portions 301 may include SOI pad regions306A, 306B, 308A, 308B, and nanowire portions 309A, 309B.

Referring to FIG. 18, in some embodiments, following the formation ofthe semiconductor on insulator (SOI) portions 301, 302, portions of thedielectric layer 303 that are under the semiconductor on insulator (SOI)portions 301, 302 are removed by an isotropic etching process that formsundercut regions, which the first and second nanowire portions 309A,309B are suspended over. The isotropic etching results in the lateraletching of portions of the dielectric layer 303 that are under thenanowire portions 309A, 309B. The lateral etch suspends the nanowireportions 309A, 309B above the dielectric layer 303. The isotropicetching of the dielectric layer 303 may be, for example, performed usinga diluted hydrofluoric acid (DHF). In one example, a 100:1 DHF etchesapproximately 2 to 3 nm of dielectric layer 303 per minute at roomtemperature. It is noted that in some embodiments, the isotropic etchprocess may be omitted so that the nanowire portions 309A, 309B have abottom surface that is in direct contact with the upper surface of thedielectric layer 303.

Still referring to FIG. 18, the nanowire portions 309A, 309B aresmoothed to form elliptical shaped (and in some cases, cylindricalshaped) nanowires. In one embodiment, the smoothing of the nanowireportions 309A, 309B may be performed by annealing of the nanowireportions 309A, 309B in hydrogen. Example annealing temperatures mayrange from 600° C. to 1000° C. In one example, the hydrogen pressure ofthe process to smooth the nanowire portions 309A, 309B ranges from 600torr to 7 torr.

In another embodiment, the reduction of the dimensions of the nanowireportions 309A, 309B may be provided by a high temperature oxidation ofthe nanowire portions 309A, 309B followed by etching of the grown oxide.The oxidation and etching process may be repeated to achieve a desirednanowire dimensions. In one embodiment, the diameter of a circularnanowire portion 309A, 309B is less than 30 nm. In another embodiment,the diameter of the circular nanowire portion 309A, 309B ranges from 2nm to 15 nm. In yet another, embodiment, the diameter of the circularnanowire portions 309A, 309B ranges from 5 nm to 10 nm.

FIG. 19 depicts one embodiment of forming a first gate structure 402A indirect contact with the first nanowire portion 309A of the first SOIportion 301, and a second gate structure 402B in direct contact with thesecond nanowire portion 309B of the second SOI portion 302. Each of thefirst and second gate structures 402A, 402B include at least one gatedielectric 311A, 311B and at least one gate conductor 312A, 312B. In theembodiments in which the first and second nanowire portions 309A, 309Bare suspended over the dielectric layer 303, the at least one gatedielectric 311A, 311B is formed around the entirety of thecircumference, i.e., over and around, of the first and second nanowireportions 309A, 309B. In the embodiments, in which the first and secondnanowire portions 309A, 309B are present on an upper surface of thedielectric layer 303, the at least one gate dielectric 311A, 311B isformed over the exposed portion of the first and second nanowireportions 309A, 309B that are not in direct contact with the dielectriclayer 303. The positioning of the at least one gate dielectric 311A,311B separates the first and second nanowire portions 309A, 309B fromthe gate conductors 312A, 312B. In one example, the at least onedielectric layer 311A, 311B may be composed of at least one of SiO₂,SiON, or HfO₂ (or other hi-K material). It is noted that the material,thickness and deposition method for the at least one dielectric layer311A, 311B is similar to the first and second gate dielectric 39, 43that are described above with reference to FIG. 1. Therefore, thedescription of the first and second gate dielectric 39, 43 of thestructure depicted in FIG. 1, is equally applicable to the at least onedielectric layer 311A, 311B that is depicted in FIG. 19.

A first gate conductor 312A is present on the first gate dielectric311A, and a second gate conductor 312B is present on the second gatedielectric 311B. In one embodiment, the first and second gate conductors312A, 312B are composed of doped polysilicon. Doping the polysiliconwith impurities, such as boron (p-type), or phosphorus (n-type), makesthe first and second gate conductors 312A, 312B conductive. It is notedthat the material, thickness and deposition method for forming the firstand second gate conductors 312A, 312B is similar to the at least onegate conductor 37, 42 that is described above with reference to FIG. 1.Therefore, the description of the at least one gate conductor 37, 42 ofthe structure depicted in FIG. 1, is equally applicable to first andsecond gate conductor 312A, 312B that is described in FIG. 19.

The first and second gate structures 402A, 402B may be capped with adielectric cap 313A, 313B. The dielectric cap 313A, 313B may function asa hard mask for each of the first and second gate structures 402A, 402Band may facilitate etch process steps to form the first and second gatestructures 402A, 402B. It is noted that the material, thickness anddeposition method for forming the dielectric cap 313A for the structuredepicted in FIG. 19 is similar to the dielectric cap 38 that isdescribed above with reference to FIG. 1. Therefore, the description ofthe dielectric cap 38 of the structure depicted in FIG. 1, is equallyapplicable to the dielectric cap 38 that is described in FIG. 19.Although not depicted in the supplied figures, a metal nitride layer,such as, for example, TaN or TiN, may be present between the first andsecond gate conductors 312A, 312B and the first and second gatedielectrics 311A, 311B.

FIG. 20 illustrates one embodiment of forming sidewall spacers 314A,314B along the sidewalls of the first and second gate structures 402A,402B. The spacers 314A, 314B are formed by depositing a blanketdielectric film such as silicon nitride and etching the dielectric filmwith an anisotropic etch, such as RIE. The spacers 314A, 314B are formedaround and over the first and second gate structure 402A, 402B. It isnoted that the material, and thickness of the sidewalls spacers 314A,314B for the structure depicted in FIG. 19 is similar to the firstsidewall spacers 11 that are described above with reference to FIG. 1.Therefore, the description of the first sidewall spacers 11 of thestructure depicted in FIG. 1, is equally applicable to the sidewallsspacers 314A, 314B that are depicted in FIG. 20.

FIG. 21 depicts one embodiment of depositing a first material layer 307doped with the first conductivity type dopant on the first SOI portion301 and the second SOI portion 302 of the substrate. In one embodiment,in which the semiconductor device being formed in the first SOI region301 of the substrate is a p-type nanowire semiconductor device, thefirst conductivity type dopant of the first material layer 307 is ap-type dopant, including but not limited to, boron, aluminum, galliumand indium. The first material layer 307 may be composed of any materialthat can carry the first type dopant and is capable of diffusing thefirst type dopant into the underlying nanowire portion 309A of the firstSOI portion 301. In one embodiment, the first material layer 307 may becomposed of a dielectric material, such as an oxide, nitride oroxynitride material. In another embodiment, the first material layer 307is a semiconductor material, such as polysilicon or single crystalsilicon. In one example, the first material layer 307 is composed of asilicate glass, such as a boron doped silicate glass.

In one embodiment, the first material layer 307 is blanket depositedatop the structure depicted in FIG. 20 including the first nanowireportion 309A of the first SOI portion 301, and the second nanowireportion 309B of the second SOI portion 302. The first material layer 307may be deposited using chemical vapor deposition (CVD) including, butnot limited to, Atmospheric Pressure CVD (APCVD), Low Pressure CVD(LPCVD) and Plasma Enhanced CVD (EPCVD), Metal-Organic CVD (MOCVD) andcombinations thereof. Other deposition methods that are suitable fordepositing the first material layer 307 include, but are not limited to:spinning from solution, spraying from solution, chemical sputterdeposition, reactive sputter deposition, ion-beam deposition, andevaporation. In one embodiment, the first material layer 307 isdeposited using a conformal deposition process. The thickness of thefirst material layer 307 may range from 1 nm to 25 nm. In oneembodiment, the thickness of the first material layer 307 ranges from 5nm to 10 nm.

In one embodiment, the first conductivity type dopant is introduced tothe first material layer 307 during the deposition process that formsthe first material layer 307. In another embodiment, the firstconductivity type dopant is introduced to the first material layer 307after its deposition using ion implantation. The concentration of thefirst conductivity type dopant in the first material layer 307 may rangefrom 1×10¹⁹ atoms/cm³ to 3×10²² atoms/cm³. In another embodiment, theconcentration of the first conductivity type dopant in the firstmaterial layer 307 may range from 1×10²⁰ atoms/cm³ to 1×10²² atoms/cm³.In yet another embodiment, the concentration of the first conductivitytype dopant in the first material layer 307 may range from 2×10²¹atoms/cm³ to 5×10²¹ atoms/cm³.

FIG. 21 further depicts forming at least one dielectric layer 319 on thefirst material layer 307. In one embodiment, the at least one dielectriclayer 319 may be formed on the first material material layer 307overlying both the first SOI portion 301 and the second SOI portion 302.The at least one dielectric layer 319 may be formed by a thermal growthprocess such as, for example, oxidation, nitridation or oxynitridation.The at least one dielectric layer 319 may also be formed by a depositionprocess such as, for example, chemical vapor deposition (CVD),plasma-assisted CVD, metal organic chemical vapor deposition (MOCVD),atomic layer deposition (ALD), evaporation, reactive sputtering,chemical solution deposition and other like deposition processes. In oneembodiment, the at least one dielectric layer 319 is deposited using aconformal deposition process. The at least one dielectric layer 319 maybe composed of an oxide, nitride or oxynitride material. It is notedthat the material, and thickness of the at least one dielectric layer319 for the structure depicted in FIG. 21 is similar to the at least onedielectric layer 9 that is described above with reference to FIG. 2.Therefore, the description of the least one dielectric layer 9 of thestructure depicted in FIG. 2, is equally applicable to the least onedielectric layer 319 that is depicted in FIG. 21.

FIG. 22 depicts one embodiment of forming a block mask 370 on the atleast one dielectric layer 319 over the first SOI portion 301, andetching an exposed portion of the at least one dielectric layer 319 andan underlying portion of the first material layer 307 selective to theblock mask 370 to expose at least the nanowire portion 309B in thesecond region of the substrate containing the second SOI portion 302. Inone embodiment, the block mask 370 is formed protecting the portion ofthe at least one dielectric layer 3199 and the first material layer 307that are present over the first SOI portion in which at least one p-typenanowire semiconductor device is subsequently formed. The exposedportion of the at least one dielectric layer 3199 and the first materiallayer 307 that are not protected by the block mask 370 are subsequentlyremoved.

The block mask 370 may comprise soft and/or hardmask materials and canbe formed using deposition, photolithography and etching. It is notedthat the material, thickness and method of producing of the block mask370 depicted in FIG. 22 is similar to the block mask 70 that isdescribed above with reference to FIG. 3. Therefore, the description ofthe block mask 370 depicted in FIG. 3, is equally applicable to theblock mask 370 that is described with reference to FIG. 22.

In one embodiment, following the formation of the block mask 370, aselective etch process may be utilized to remove the exposed portion ofthe at least one dielectric layer 319 and the first material layer 307.In one embodiment, the selective etch process includes a first etchchemistry for removing the exposed portion of the at least onedielectric layer 319 selective to the underlying portion of the firstmaterial layer 307 and selective to the block mask 370. A second etchchemistry may then remove the exposed portion of the first materiallayer 307 selective to the underlying portion of the second nanowireportion 309B of the second SOI portion 302, and selective to the blockmask 370. The second etch chemistry is also selective to the second gatestructure 402B and the sidewall spacers 314B that are present adjacentto the second gate structure 402B.

FIG. 23 depicts one embodiment of removing the block mask 370 anddepositing the second material layer 320 doped with the secondconductivity type dopant in direct contact with a remaining portion ofthe at least one dielectric layer 319 that is present on the first SOIportion 301 and in direct contact with the second nanowire portion 309Bof the second SOI portion 302 in the second region of the substrate. Thesecond conductivity type dopant is an opposite conductivity type as thefirst conductivity type dopant. For example, when the first conductivitytype dopant is p-type, the second conductivity type dopant is n-type.The block mask 370 may be removed by selective etch processes, chemicalstrip methods, oxygen ashing or combinations thereof.

In one embodiment, in which the semiconductor device being formed fromthe second SOI portion 302 is an n-type nanowire semiconductor device,the second conductivity type dopant of the second material layer 320 isan n-type dopant. In a second SOI portion 302 that is composed ofsilicon, examples of n-type dopants include, but are not limited to,antimony, arsenic and phosphorous. The second material layer 320 may becomposed of any material that can carry the second type dopant and iscapable of diffusing the second type dopant into the underlying secondnanowire portion 309B of the second SOI portion 302. In one embodiment,the second material layer 320 may be composed of a dielectric material,such as an oxide, nitride or oxynitride material. In another embodiment,the second material layer 320 is a semiconductor material, such aspolysilicon or single crystal silicon. In one example, the secondmaterial layer 320 is composed of a silicate glass, such as a borondoped silicate glass.

The second material layer 320 may be deposited using chemical vapordeposition (CVD) including, but not limited to, Atmospheric Pressure CVD(APCVD), Low Pressure CVD (LPCVD) and Plasma Enhanced CVD (EPCVD),Metal-Organic CVD (MOCVD) and combinations thereof may also be employed.Other deposition methods that are suitable for depositing the secondmaterial layer 320 include, but are not limited to: spinning fromsolution, spraying from solution, chemical sputter deposition, reactivesputter deposition, ion-beam deposition, and evaporation. In oneembodiment, the second material layer 320 is deposited using a conformaldeposition process. The thickness of the second material layer 320 mayrange from 1 nm to 25 nm. In one embodiment, the thickness of the secondmaterial layer 320 ranges from 5 nm to 10 nm.

In one embodiment, the second conductivity type dopant is introduced tothe second material layer 320 during the deposition process that formsthe second material layer 320. In another embodiment, the secondconductivity type dopant is introduced to the second material layer 320after its deposition using ion implantation. The concentration of thesecond conductivity type dopant in the second material layer 320 mayrange from 1×10¹⁹ atoms/cm³ to 3×10²² atoms/cm³. In another embodiment,the concentration of the second conductivity type dopant in the secondmaterial layer 8 may range from 1×10²⁰ atoms/cm³ to 1×10²² atoms/cm³. Inyet another embodiment, the concentration of the second conductivitytype dopant in the second material layer 8 may range from 2×10²¹atoms/cm³ to 5×10²¹ atoms/cm³.

FIG. 24 depicts one embodiment of driving the first conductivity dopantfrom the first material layer 307 into the first nanowire portion 309Aof the first SOI portion 301, and driving the second conductivity typedopant from the second material layer 320 into the second nanowireportion 309B of the second SOI portion 302. The first and secondconductivity dopant being introduced to the first and second nanowireportions 309A, 309B provide the source and drain extension regions ofthe n-type and p-type nanowire devices that are formed from the firstand second SOI portions 301, 302. In one embodiment, the dopant from thefirst material layer 307 and second material layer 320 is diffused intothe nanowire portions 309A, 309B of the first and second SOI portions301, 302 by an annealing processes including, but not limited to: rapidthermal annealing, furnace annealing, flash lamp annealing or laserannealing. In one embodiment, the thermal annealing is conducted at atemperature ranging from 850° C. to 1350° C.

In one embodiment, in which the first conductivity type dopant in thefirst material layer 307 is a p-type dopant, the source extension regionand drain extension region that are formed in the first nanowire portion309A of the first SOI portion 301 have a p-type conductivity. Typically,the dopant concentration of the source extension region and drainextension region having the p-type conductivity ranges from 1×10¹⁹atoms/cm³ to 5×10²¹ atoms/cm³. In another embodiment, the sourceextension region and drain extension region having the p-typeconductivity ranges from 4×10¹⁹ atoms/cm³ to 4×10²⁰ atoms/cm³.

In one embodiment, in which the second conductivity type dopant in thesecond material layer 320 is doped to an n-type conductivity, the sourceextension region and drain extension region that are formed in thesecond nanowire portion 309B of the second SOI portion 302 have ann-type conductivity. Typically, the dopant concentration of the sourceextension region and drain extension region having the n-typeconductivity ranges from 1×10¹⁹ atoms/cm³ to 1×10²¹ atoms/cm³. Inanother embodiment, the source extension region and drain extensionregion having the n-type conductivity ranges from 4×10¹⁹ atoms/cm³ to4×10²⁰ atoms/cm³.

The above process scheme provides a nanowire semiconductor device thatdoes not use ion implantation to provide the source and drain extensionregions of the device. In one embodiment, the method disclosed hereinovercomes the disadvantages that result from ion implantation by formingthe source and drain extension regions in the nanowire portions 309A,309B using a material layer, such as a dielectric material layer, tocarry the dopant for the extension source and drain regions followed byan annealing process, wherein the annealing process drives the dopantinto the nanowire structure to form extension source and drain regions.This provides source and drain extension regions within the nanowireportions 309A, 309B having a damage-free crystal structure. The term“damage-free” means that a single crystal lattice structure is presentthroughout the entirety of the source and drain extension regions thatare present in the nanowire portions 309A, 309B.

Although not shown in the Figures, the SOI pad regions 306A, 306B, 308A,308B may be ion implanted to provide deep source regions and deep drainregions of the device. The deep source and drain regions have the sameconductivity dopant as the source and drain extension regions, but thedeep source and drain regions typically have a greater dopantconcentration then the source and drain extension regions. In anotherembodiment, raised source and drain regions may be formed on the SOI padregions 306A, 306B, 308A, 308B. The raised source and drain regions havethe same conductivity dopant as the source and drain extension regions,but the raised source and drain regions typically have a greater dopantconcentration then the source and drain extension regions. A metalsemiconductor alloy, such as a silicide, may be formed on the uppersurface of the SOI pad regions 306A, 306B, 308A, 308B, or the raisedsource and drain regions. Following the formation of the metalsemiconductor alloy, back end of the line (BEOL) processing may beemployed to provide connectivity to the device.

While this invention has been particularly shown and described withrespect to preferred embodiments thereof, it will be understood by thoseskilled in the art that the foregoing and other changes in forms anddetails may be made without departing from the spirit and scope of thepresent invention. It is therefore intended that the present inventionnot be limited to the exact forms and details described and illustrated,but fall within the scope of the appended claims.

What is claimed is:
 1. A semiconductor device comprising: a gatestructure on a first portion of a semiconductor layer having a thicknessof less than 10 nm; source and drain regions in the semiconductor layeron opposing sides of the first portion of semiconductor layer that thegate structure is present on, wherein the source and drain regionsextend to an entire thickness of the semiconductor layer, wherein acrystal structure of the source and drain regions in the semiconductorlayer is damage-free.
 2. The semiconductor device of claim 1, whereinthe semiconductor layer is a semiconductor on insulator (SOI) layer of asemiconductor on insulator (SOI) substrate.
 3. The semiconductor deviceof claim 2, wherein the SOI substrate further comprises strain inducingwells on opposing sides of the gate structure, wherein the straininducing wells induces a compressive strain or a tensile strain on achannel region of the device.
 4. The semiconductor device of claim 1,wherein the semiconductor device is a field effect transistor (FET). 5.The semiconductor device of claim 2, wherein the SOI layer is comprisedof a semiconductor material selected from the group consisting of Si,strained Si, SiC, SiGe, SiGeC, Si alloys, Ge, Ge alloys, GaAs, InAs,InP, and a combination thereof.
 6. The semiconductor device of claim 2,wherein the gate structure includes at least one gate dielectric that ispresent on the SOI layer and at least one gate conductor that is presenton the at least one gate dielectric.
 7. The semiconductor device ofclaim 6, wherein the at least one gate conductor is composed of a metalselected from the group consisting of W, Ni, Ti, Mo, Ta, Cu, Pt, Ag, Au,Ru, Ir, Rh, and Re, and combinations thereof.
 8. The semiconductordevice of claim 1, wherein the source region and the drain region aredoped to a p-type or an n-type conductivity.
 9. The semiconductor deviceof claim 1, wherein the at least one gate dielectric is a dielectricmaterial that is selected from the group consisting of SiO₂, HfO₂, ZrO₂,Al₂O₃, TiO₂, La₂O₃, SrTiO₃, LaAlO₃, Y₂O₃ and mixtures thereof.
 10. Thesemiconductor device of claim 1, wherein the semiconductor layer is ananowire.
 11. The semiconductor device of claim 1, wherein a metalsemiconductor alloy is present on the source and drain regions.
 12. Thesemiconductor device of claim 1, wherein a raised source region and araised drain region are present on the source and drain regions.
 13. AfinFET device comprising: a gate structure on a portion of a finstructure having a width of less than 10 nm, the fin structure includinga dielectric cap present on a semiconductor material, wherein exposedportions of the fin structure are on opposing sides of the gatestructure; and source and drain extension regions in the semiconductormaterial of the fin structure on opposing sides of the gate structure ispresent on, wherein the source and drain extension have a crystal thatis damage-free.
 14. The finFET device of claim 13, wherein the finstructure is comprised of a semiconductor material selected from thegroup consisting of Si, strained Si, SiC, SiGe, SiGeC, Si alloys, Ge, Gealloys, GaAs, InAs, InP, and a combination thereof.
 15. The finFETdevice of claim 13, wherein the gate structure includes at least onegate dielectric that is present on the fin structure and at least onegate conductor that is present on the at least one gate dielectric. 16.The finFET device of claim 13, wherein the at least one gate conductoris composed of a metal selected from the group consisting of W, Ni, Ti,Mo, Ta, Cu, Pt, Ag, Au, Ru, Ir, Rh, and Re, and combinations thereof.17. The finFET device of claim 13, wherein the source extension regionand the drain extension region are doped to a p-type or an n-typeconductivity.
 18. The finFET device of claim 13, wherein the at leastone gate dielectric is a dielectric material that is selected from thegroup consisting of SiO₂, HfO₂, ZrO₂, Al₂O₃, TiO₂, La₂O₃, SrTiO₃,LaAlO₃, Y₂O₃ and mixtures thereof.